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Renesas R5F565N4AGLK#20
- Part No.:
- R5F565N4AGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F565N4AGLK#20.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F565N4AGLK#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, Ethernet MAC, CAN 2.0B, SD host/slave, QSPI, and hardware AES-128/192/256 encryption - deployed in industrial HMI gateways requiring real-time control, secure connectivity, and graphics acceleration.
For engineers reviewing the R5F565N4AGLK#20 datasheet, R5F565N4AGLK#20 pinout, R5F565N4AGLK#20 application, or R5F565N4AGLK#20 equivalent, key selection considerations include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +85°C operating range (D-version), dual-bank flash for safe firmware updates, GLCDC + DRW2D for embedded GUIs, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565N4AGLK#20 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, supporting little-endian or big-endian data arrangement and ultra-compact variable-length instructions. It integrates a single-precision IEEE-754 FPU, two MAC units, and a 32-bit multiplier with one-cycle execution at 120 MHz.
Its clock system combines external crystal (8–24 MHz) or internal HOCO/LOCO oscillators with PLL synthesis, delivering ICLK up to 120 MHz, PCLKA up to 120 MHz (for ETHERC, GLCDC, DRW2D), and PCLKB up to 60 MHz (for timers, ADC, UART). Peripheral clocks are independently configurable, enabling precise power/performance trade-offs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic response in motor control and protocol stacks |
| Memory | 2 MB dual-bank code flash (enables background programming and safe OTA updates), 640 KB SRAM (256 KB main + 384 KB expansion), 32 KB data flash (100k erase cycles) |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), 2-channel 12-bit D/A, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), 2× CAN 2.0B (32 mailboxes/channel), 13× SCI (UART/SPI/I²C modes), 3× RSPI, 1× QSPI, SDHI/SDSI/MMCIF, USB 2.0 FS host/function/OTG |
| Graphics & Display | Graphic-LCD controller (GLCDC) supporting 3-plane overlay, 2D drawing engine (DRW2D) with vector/bit-blit acceleration, 32-/16-/8-bit pixel formats |
| Security & Safety | AES-128/192/256, Trusted Secure IP (TSIP), MPU (8 regions), CRC calculator (8/32-bit), IWDT with window function, register write protection, IEC60730 compliance support |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for ADC/DAC operation |
| XTAL / EXTAL | Main clock oscillator terminals | Supports 8–24 MHz crystal for high-accuracy timing; required for Ethernet PHY synchronization and USB clock recovery |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC interface for PHY configuration and status monitoring |
| ETH_TXD0–3 / ETH_RXD0–3 | Ethernet data lanes | 4-bit transmit/receive bus for MII mode; supports RMII with reduced pin count (2-bit + REF_CLK) |
| CAN0_TX / CAN0_RX | Channel 0 CAN transceiver I/O | Differential signaling pins compliant with ISO 11898-1; support 1 Mbps baud rate with built-in filtering |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); enables direct boot from SD card or firmware storage |
| QSPI_IO0–3 / QSPI_CLK / QSPI_SSL | Quad SPI interface | Supports x1/x2/x4 I/O modes for fast serial flash memory access; used for external program/data storage or XIP |
| GLCD_D0–23 / GLCD_HSYNC / VSYNC / DE | Graphic LCD interface | 24-bit RGB parallel output with sync signals; drives TFT panels up to WVGA resolution without external controller |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating system downtime |
| Integrated GLCDC + DRW2D | Reduces BOM cost and PCB area by replacing external display controllers; supports layered UI rendering with alpha blending |
| IEC60730-compliant safety suite | Includes oscillation-stop detection, CRC calculation, IWDT windowing, self-diagnostic A/D, and register lock bits for Class B appliance certification |
| Flexible clock domain partitioning | Independent ICLK (120 MHz), PCLKA (120 MHz), PCLKB (60 MHz), PCLKC/D (60 MHz) allow per-peripheral power/performance tuning |
| Event Link Controller (ELC) | Hardware interconnect bypasses CPU for timer-triggered ADC sampling, PWM dead-time insertion, or GPIO state changes - reduces latency and ISR overhead |
Applications
| Industrial HMI Gateway | Secure Edge Node |
|---|---|
Use Scenario: Embedded gateway aggregating Modbus RTU/ASCII fieldbus data, converting to MQTT/HTTP over Ethernet or cellular, with local touchscreen display. IC Role / Device Role / Timing Role: Central application processor executing RTOS, protocol stacks (TCP/IP, TLS, Modbus), GLCDC-driven UI, and cryptographic offload via TSIP/AES. Use Value: Dual-bank flash enables zero-downtime field updates; integrated Ethernet + CAN + SDIO eliminates external PHY/transceivers; DRW2D accelerates dynamic chart rendering. | Use Scenario: UL/IEC-certified smart energy meter with tamper detection, secure firmware update, and local LCD display showing consumption metrics. IC Role / Device Role / Timing Role: Safety-critical controller managing metrology ADC sampling, RTC-based billing intervals, encrypted data logging to SD, and secure boot verification. Use Value: IEC60730 features (IWDT windowing, CRC, register protection) satisfy Class B requirements; temperature sensor monitors die temp for calibration compensation; AES-256 secures firmware images. |
| Medical Patient Monitor | Automated Test Equipment (ATE) |
Use Scenario: Portable vital-signs monitor capturing ECG, SpO₂, and temperature, displaying waveforms and trends on color LCD, storing logs to SD card. IC Role / Device Role / Timing Role: Real-time signal acquisition hub synchronizing analog front-end sampling, processing FFTs via FPU, rendering graphics via GLCDC, and managing non-volatile storage. Use Value: 12-bit dual A/D with self-diagnostic ensures signal integrity; 640 KB SRAM buffers multi-channel waveform data; SDHI supports high-speed log export. | Use Scenario: Rack-mounted test instrument performing automated calibration of sensors and actuators using precision DAC outputs, timed GPIO triggers, and high-speed data capture. IC Role / Device Role / Timing Role: Precision timing controller generating synchronized PWM, DAC waveforms, and trigger pulses while acquiring responses via high-speed ADC and SPI peripherals. Use Value: MTU3+TPU timers deliver sub-microsecond PWM edge control; 12-bit R12DA provides calibrated analog stimulus; ELC links timer events to ADC start for jitter-free capture. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFLK#20 | Same RX65N Group, identical 176-pin LFBGA package, but 1.5 MB flash, 256 KB SRAM, and no GLCDC/DRW2D | Lacks graphics acceleration and full Ethernet MAC; suitable for headless industrial controllers without display | Select when GUI capability is unnecessary and lower memory cost is prioritized |
| R5F566TEADFP#30 | RX66T Group part in 144-pin LQFP; 160 MHz CPU, 1 MB flash, 256 KB SRAM, enhanced motor control timers (MTU3+), no Ethernet or SD interfaces | Optimized for servo/inverter control with advanced PWM dead-time and encoder capture; no networking or display subsystems | Select for high-performance motor drive applications where Ethernet/graphics are irrelevant |
Compared with R5F565N4AGLK#20, R5F565NEDFLK#20 reduces graphics and memory capacity for cost-sensitive headless nodes, while R5F566TEADFP#30 trades networking/display for higher-frequency motor control peripherals - neither offers pin compatibility or identical feature set.
Availability
R5F565N4AGLK#20 is available at Aetrix Electronics and suitable for industrial HMI gateways, secure edge nodes, medical patient monitors, and automated test equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F565N4AGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group - to which R5F565N4AGLK#20 belongs - was designed for high-integration industrial and building automation applications demanding real-time performance, functional safety, rich connectivity, and embedded graphics capabilities.
FAQ
What is the maximum operating frequency and CPU performance of the R5F565N4AGLK#20?
The R5F565N4AGLK#20 operates at a maximum system clock frequency of 120 MHz using its RXv2 CPU core and delivers 240 DMIPS of computational throughput. Its single-precision IEEE-754 floating-point unit (FPU), dual MAC units, and one-cycle 32-bit multiplier enable deterministic real-time processing for control algorithms, signal analysis, and graphics rendering - all verified in the official Renesas R01DS0276EJ0240 datasheet.
Does the R5F565N4AGLK#20 support secure firmware updates and IEC60730 compliance?
Yes, the R5F565N4AGLK#20 includes multiple hardware features for secure firmware updates and IEC60730 Class B compliance: dual-bank flash memory enables background programming and safe bank-swapping, Trusted Secure IP (TSIP) accelerates AES-128/192/256 encryption, CRC calculator supports 8/32-bit polynomials, independent watchdog timer (IWDT) with windowing, register write protection, and self-diagnostic A/D functionality - all documented in the R01DS0276EJ0240 specification.
What display interfaces and graphics acceleration does the R5F565N4AGLK#20 provide?
The R5F565N4AGLK#20 integrates a full-featured Graphic-LCD Controller (GLCDC) supporting 24-bit RGB parallel output, three-layer plane composition (background, graphic 1, graphic 2), and CLUT-based color conversion, plus a dedicated 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing, bit-blitting, rotation, and scaling. These peripherals eliminate the need for external display controllers in embedded HMI designs - confirmed in Section 1.1 and Table 1.1 of the R01DS0276EJ0240 datasheet.
Which communication interfaces are included in the R5F565N4AGLK#20 for industrial networking?
The R5F565N4AGLK#20 integrates Ethernet MAC (10/100 Mbps, MII/RMII), two CAN 2.0B channels (32 mailboxes each), 13 serial channels (SCIg/h/i supporting UART/SPI/I²C modes), three RSPI ports, one QSPI port, SD host/slave (SDHI/SDSI), and USB 2.0 FS host/function/OTG - enabling converged industrial networking with deterministic fieldbus (CAN), wired IP (Ethernet), removable storage (SD), and human interface (USB). This full suite is detailed in Tables 1.1 and 1.2 of the R01DS0276EJ0240 datasheet.
What is the package type and thermal specification of the R5F565N4AGLK#20?
The R5F565N4AGLK#20 uses the PLQP0176KB-A package: a 176-pin Low-Profile Quad Flat Package (LFBGA) measuring 24 mm × 24 mm with 0.5 mm pitch and an exposed thermal pad. It is rated for industrial temperature range (–40°C to +85°C), designated as the 'D-version' per Renesas documentation - explicitly listed in the "Package Information" section of the R01DS0276EJ0240 datasheet Rev.2.40.
R5F565N4AGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N4AGLK#20 FAQ
1.How can I place an order for R5F565N4AGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N4AGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N4AGLK#20 reliable?
The price and inventory of R5F565N4AGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N4AGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F565N4AGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N4AGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N4AGLK#20?
R5F565N4AGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N4AGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N4AGLK#20?
For technical support, including R5F565N4AGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N4AGLK#20 requirements.
6.How does Aetrix verify that R5F565N4AGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F565N4AGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N4AGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F565N4AGLK#20?
All R5F565N4AGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N4AGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N4AGLK#20 part is unused and in its original packaging.
Return procedure for R5F565N4AGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N4AGLK#20 Tags
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