Renesas R5F565N4BGFP#10
- Part No.:
- R5F565N4BGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N4BGFP#10.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F565N4BGFP#10 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz, delivering 240 DMIPS with integrated single-precision IEEE-754 FPU, 2 MB on-chip code flash, 640 KB SRAM (no wait states), and dual-bank flash for safe firmware updates. It integrates Ethernet MAC, CAN 2.0B (2 channels), SD host/slave, QSPI, GLCDC, DRW2D, and hardware AES-128/192/256 - targeting industrial HMI, networked gateway, and secure embedded control applications.
For engineers reviewing the R5F565N4BGFP#10 datasheet, R5F565N4BGFP#10 pinout, R5F565N4BGFP#10 application, or R5F565N4BGFP#10 equivalent, key selection considerations include its 176-pin LFBGA package (PLQP0176KB-A), 120-MHz real-time performance with MPU and TSIP security, Ethernet + CAN coexistence, and support for graphical LCDs with 2D acceleration - all within –40°C to +105°C extended temperature operation.
Technical Context
The R5F565N4BGFP#10 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It supports little-endian or big-endian data arrangement and includes two 72-bit accumulators, a 32×32→64-bit multiplier, and a 32/32→32-bit divider with one- and two-cycle execution respectively.
Its clock system combines external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL for flexible domain partitioning: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/EDMAC/AES/GLCDC/DRW2D, and PCLKB up to 60 MHz for most peripherals including S12AD units and MTU3 timers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic response in motor control and protocol stacks |
| Memory | 2 MB code flash (dual-bank), 640 KB SRAM (256 KB main + 384 KB expansion), 32 KB data flash (100k erase cycles) |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A channels, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC (10/100 Mbps MII/RMII), CAN 2.0B (2 channels, 32 mailboxes each), USB 2.0 FS host/function/OTG, SDHI/SDSI/MMCIF |
| Graphics & Imaging | Graphic-LCD controller (GLCDC) supporting 3-plane overlay, 2D drawing engine (DRW2D) with vector/bit-blit acceleration |
| Security | Trusted Secure IP (TSIP), AES-128/192/256, CRC calculator (8-/32-bit), memory protection unit (MPU, 8 regions) |
Pinout & Package
R5F565N4BGFP#10 uses the PLQP0176KB-A package: 176-pin LFBGA, 24 mm × 24 mm, 0.5 mm pitch, –40°C to +105°C operating range (G-version). Pinout validated per Renesas R01DS0276EJ0240 Rev.2.40, pages 13–15 (pin function mapping) and page 183 (package outline).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital domains enable noise isolation for ADC/DAC accuracy |
| XTAL / EXTAL | Main clock oscillator terminals | Support 8–24 MHz crystal for precise timing; required for Ethernet and USB clock recovery |
| ETH_MDC / ETH_MDIO | MDIO management interface | Enables PHY configuration and status monitoring over shared bus without dedicated GPIO |
| ETH_TXD0–3 / ETH_RXD0–3 | Ethernet data lanes | Supports MII (4-bit TX/RX) or RMII (2-bit TX/RX + REF_CLK); pin-strapped mode selection |
| CAN0_TX / CAN0_RX | Channel 0 differential CAN bus interface | Direct connection to ISO 11898-1 compliant transceiver; no external level-shifting needed |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 1- or 4-bit SD bus supporting high-speed mode (25 MB/s); integrated pull-ups reduce BOM count |
| GLCD_D0–23 | RGB parallel display data bus | 24-bit true-color interface driving TFT panels up to WXGA resolution via GLCDC controller |
| DRW2D_VSYNC / DRW2D_HSYNC | 2D engine synchronization outputs | Coordinate frame rendering with display timing; enable tear-free UI updates in embedded HMI |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables background programming and seamless firmware update without halting application execution |
| Trusted Secure IP (TSIP) | Hardware-accelerated AES and key management protect firmware integrity and secure boot against cloning |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - e.g., TPU trigger → A/D conversion → DMA transfer |
| Integrated GLCDC + DRW2D | Offloads CPU from pixel manipulation: 2D engine handles rotation, scaling, alpha blending, and CLUT-based color conversion |
| IEC 60730 safety support | Oscillation-stop detection, CRC calculation, IWDT windowing, and register write protection meet Class B requirements |
| Flexible power domains | Four low-power modes (sleep, software standby, deep software standby) with RTC and 8 KB standby RAM retention |
Applications
| Industrial HMI Gateway | Secure Networked PLC |
|---|---|
Use Scenario: Standalone panel PC controlling field devices via CAN and Modbus TCP over Ethernet. IC Role / Device Role / Timing Role: Central application processor executing RTOS, managing dual-network stack (CAN + Ethernet), rendering GUI via GLCDC/DRW2D, and performing real-time I/O scanning. Use Value: Single-chip integration eliminates external graphics controller and crypto accelerator; 120 MHz CPU ensures <100 µs cycle time for motion control loops. |
Use Scenario: DIN-rail mounted programmable logic controller with web-based configuration and secure remote firmware update. IC Role / Device Role / Timing Role: Safety-certified controller running IEC 61131-3 runtime, enforcing secure boot with TSIP, and validating firmware signatures before execution. Use Value: Built-in MPU, CRC, IWDT, and register lock prevent unauthorized code injection; dual-bank flash enables fail-safe OTA updates. |
| Medical Data Logger | Smart Energy Meter |
Use Scenario: Battery-powered patient monitor acquiring ECG/SpO₂ via analog front-end and storing encrypted logs to SD card. IC Role / Device Role / Timing Role: Signal acquisition hub with 12-bit dual A/D, temperature-compensated reference, AES-encrypted storage, and low-power deep standby between readings. Use Value: On-chip 32 KB data flash withstands 100,000 erase cycles for lifetime logging; 0.19 mA/MHz active current extends battery life. |
Use Scenario: Revenue-grade meter communicating via CAN (to sensors) and Ethernet (to utility head-end) while meeting IEC 62056 and DLMS/COSEM standards. IC Role / Device Role / Timing Role: Protocol gateway with hardware-assisted TLS handshake (via TSIP), precision RTC for tariff switching, and tamper-detection GPIOs. Use Value: Integrated Ethernet MAC + CAN eliminates external PHY/transceiver; RTC with leap-year correction ensures accurate billing intervals. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, identical 176-pin LFBGA package, but 1.5 MB flash / 256 KB SRAM (vs. 2 MB / 640 KB) | Suitable for cost-sensitive designs where full memory capacity is not required; lacks expansion RAM for large frame buffers | Select when GUI complexity is limited and BOM cost reduction outweighs future scalability needs. |
| R5F566TEBDFP#30 | RX66T Group part: higher 160 MHz CPU, enhanced MTU3 for motor control, but no Ethernet MAC or GLCDC | Optimized for servo drives and inverters; lacks networking and graphics - not interchangeable for HMI or gateway use | Choose only for real-time motor control applications requiring advanced PWM dead-time compensation and encoder interfaces. |
Compared with R5F565N4BGFP#10, R5F565NEDFP#30 offers identical footprint and peripheral set at reduced memory, while R5F566TEBDFP#30 trades networking/graphics for superior motor control timing - neither is pin-compatible nor functionally substitutable without hardware and firmware redesign.
Availability
R5F565N4BGFP#10 is available at Aetrix Electronics and suitable for industrial HMI, secure networked PLCs, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and extended temperature operation.
Supply support for R5F565N4BGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group - including R5F565N4BGFP#10 - was designed for high-integration industrial applications demanding real-time performance, functional safety, connectivity, and rich human-machine interface capabilities.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565N4BGFP#10?
The R5F565N4BGFP#10 features a 32-bit RXv2 CPU core with CISC Harvard architecture and operates at a maximum frequency of 120 MHz, delivering 240 DMIPS. Its 5-stage pipeline, variable-length instructions, and dual 72-bit accumulators enable high code density and deterministic real-time execution - critical for industrial control and protocol stacks in the R5F565N4BGFP#10.
Does the R5F565N4BGFP#10 support Ethernet and CAN simultaneously, and what are the channel counts?
Yes, the R5F565N4BGFP#10 integrates one Ethernet MAC (10/100 Mbps MII/RMII) and two independent CAN 2.0B channels, each supporting 32 mailboxes. This enables concurrent networked communication - for example, CAN for fieldbus device control and Ethernet for cloud telemetry - without resource contention, a key capability confirmed in the R5F565N4BGFP#10 datasheet section 1.1.
What graphics and display capabilities does the R5F565N4BGFP#10 provide?
The R5F565N4BGFP#10 includes a Graphic-LCD Controller (GLCDC) supporting 3-plane overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) with vector drawing, bit blitting, rotation, and scaling. It drives RGB parallel displays up to WXGA resolution via 24-bit GLCD_D0–23 pins - eliminating need for external GPU in embedded HMI designs using the R5F565N4BGFP#10.
How does the R5F565N4BGFP#10 support functional safety standards like IEC 60730?
The R5F565N4BGFP#10 provides hardware features required for Class B compliance: oscillation-stop detection, CRC calculator (CRCA) for memory/data integrity, independent watchdog timer (IWDT) with windowing, register write protection, and self-diagnostic A/D functions. These are documented in the R5F565N4BGFP#10 datasheet sections 1.1 and 2.3 as part of its IEC 60730 support suite.
What is the package type, pin count, and temperature grade of the R5F565N4BGFP#10?
The R5F565N4BGFP#10 uses the PLQP0176KB-A package: 176-pin LFBGA, 24 mm × 24 mm, 0.5 mm pitch, rated for –40°C to +105°C operation (G-version). This extended temperature grade and fine-pitch BGA are specified in the R5F565N4BGFP#10 datasheet revision 2.40, page 183, and align with industrial and transportation application requirements.
R5F565N4BGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N4BGFP#10 FAQ
1.How can I place an order for R5F565N4BGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N4BGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N4BGFP#10 reliable?
The price and inventory of R5F565N4BGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N4BGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F565N4BGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N4BGFP#10 transactions.
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4.How is shipping managed for R5F565N4BGFP#10?
R5F565N4BGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N4BGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N4BGFP#10?
For technical support, including R5F565N4BGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N4BGFP#10 requirements.
6.How does Aetrix verify that R5F565N4BGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N4BGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N4BGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F565N4BGFP#10?
All R5F565N4BGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N4BGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N4BGFP#10 part is unused and in its original packaging.
Return procedure for R5F565N4BGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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