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Renesas R5F565N4BGLK#20
- Part No.:
- R5F565N4BGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F565N4BGLK#20.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F565N4BGLK#20 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 2 MB on-chip code flash, 640 KB SRAM, single-precision IEEE-754 FPU, Ethernet MAC, dual CAN channels, SD host/slave interfaces, and hardware AES/TSIP encryption. It targets industrial HMI, networked gateways, and secure edge nodes requiring real-time control with rich connectivity.
For engineers reviewing the R5F565N4BGLK#20 datasheet, R5F565N4BGLK#20 pinout, R5F565N4BGLK#20 application, or R5F565N4BGLK#20 equivalent, key selection factors include its 176-pin LFBGA package (PLQP0176KB-A), 120-MHz deterministic timing, dual-bank flash for safe firmware updates, integrated GLCDC+DRW2D for embedded graphics, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565N4BGLK#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling ultra-compact code density. It integrates a dual-bank flash memory system supporting background programming and bank-swapping during execution, critical for fail-safe OTA updates in field-deployed equipment.
Its peripheral subsystem includes an Ethernet MAC with RMII/MII support, two ISO11898-1 CAN controllers (32 mailboxes each), and a full-featured SDIO stack (SDHI + SDSI + MMCIF) enabling direct interfacing with SD cards, Wi-Fi modules, and eMMC. Clocking is managed via PLL, HOCO/LOCO oscillators, and independent PCLK domains (PCLKA up to 120 MHz for ETHERC/EDMAC/AES/GLCDC, PCLKB up to 60 MHz for timers/ADC).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure; enables background programming and zero-downtime firmware swap |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), no-wait access at 120 MHz |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, 136 GPIOs (19 with 5-V tolerance) |
| Connectivity | Ethernet MAC (10/100 Mbps), 2× CAN, 3× RSPI, 1× QSPI, 3× I²C (1× up to 1 Mbps), 13× SCI, SDHI/SDSI/MMCIF |
| Analog Peripherals | Two 12-bit ADC units (8 + 21 channels), 2× 12-bit DAC, on-die temperature sensor (±1°C) |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), MPU (8 regions), CRC calculator (8/32-bit), register write protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails; supports 2.7–3.6 V operation with internal regulation |
| XTAL / EXTAL | Main clock oscillator terminals | Supports 8–24 MHz external crystal; enables precise timing for Ethernet, USB, and RTC |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and single-chip vs. extended mode at reset release |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MDIO bus for configuring external Ethernet PHY |
| RMII_RXD0 / RMII_RXD1 / RMII_TXD0 / RMII_TXD1 / RMII_TXEN / RMII_REF_CLK | Ethernet physical layer interface | 6-pin RMII interface supporting 10/100 Mbps full/half-duplex; eliminates need for MII's 16-signal bus |
| CAN0_TX / CAN0_RX / CAN1_TX / CAN1_RX | CAN transceiver I/O | Dedicated differential signal pairs per channel; compliant with ISO11898-1 physical layer |
| SD0_CMD / SD0_CLK / SD0_DATA0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); includes card detection and write-protect sensing |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; requires external coin cell or supercapacitor |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware update without halting application execution; critical for industrial uptime requirements |
| Integrated GLCDC + DRW2D | Hardware-accelerated graphic-LCD controller and 2D drawing engine eliminate need for external GPU in HMI designs |
| IEC60730 Class B support | Includes oscillation-stop detection, CRC calculator, IWDT with window function, self-diagnostic A/D, and register write protection |
| Multi-domain clocking (PCLKA/PCLKB/PCLKC/PCLKD) | Allows independent clock scaling per peripheral group-e.g., 120 MHz for Ethernet, 60 MHz for ADC-to optimize performance/power |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention-e.g., TPU trigger → ADC start → DMA transfer → interrupt |
Applications
| Industrial HMI Panel | Secure IoT Gateway |
|---|---|
Use Scenario: Standalone touch-based operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Primary application processor managing TFT LCD display (via GLCDC/DRW2D), CAN bus communication with drives/sensors, and SD card storage of runtime logs. Use Value: Dual-bank flash allows silent firmware patching during maintenance windows; 640 KB SRAM hosts full GUI stack and real-time control logic concurrently. | Use Scenario: Edge gateway aggregating Modbus RTU, CANopen, and BACnet MS/TP fieldbus data into encrypted MQTT/TLS packets for cloud upload. IC Role / Device Role / Timing Role: Central protocol translator and security enforcer-running TLS stack on FPU, performing AES encryption via TSIP, and managing multiple concurrent fieldbus interfaces. Use Value: Hardware AES/TSIP offloads crypto processing from CPU; dual CAN + Ethernet enables simultaneous fieldbus bridging and upstream IP connectivity. |
| Networked Energy Meter | Medical Data Logger |
Use Scenario: DIN-rail mounted smart meter with pulse counting, tariff scheduling, and DLMS/COSEM over TCP/IP via Ethernet. IC Role / Device Role / Timing Role: Real-time metering controller with precise timekeeping (RTC + sub-clock), secure firmware updates (dual-bank flash), and DLMS protocol stack execution. Use Value: Independent watchdog timer (IWDT) with window function ensures deterministic recovery from faults; 120-MHz CPU handles DLMS parsing and TLS handshake within strict timing budgets. | Use Scenario: Portable patient monitor recording ECG, SpO₂, and temperature, storing 72+ hours of waveform data to SD card with tamper-proof audit trail. IC Role / Device Role / Timing Role: Safety-certified data acquisition hub-sampling analog sensors via 12-bit ADC, timestamping with RTC, encrypting logs using AES-256 before SD write. Use Value: On-die temperature sensor (±1°C) calibrates ADC offset drift; register write protection prevents accidental overwrite of critical safety configuration registers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 144-pin LFQFP package (PLQP0144KA-B), 1 MB flash, 256 KB SRAM | Limited peripheral count (e.g., 1× CAN, no SDHI), smaller footprint, lower I/O count (111 pins) | Select when board space is constrained and Ethernet/SDIO are not required; cost-sensitive industrial controls. |
| R5F566TEBGLK#20 | RX66T Group, 176-pin LFBGA, 2 MB flash, 384 KB SRAM, optimized for motor control (3× MTU3, 3× PPG, encoder interfaces) | Enhanced PWM resolution and real-time motor control peripherals; lacks Ethernet MAC and SDHI | Select for servo/inverter applications needing >100 kHz PWM and position feedback; not suitable for networking-centric designs. |
Compared with R5F565N4BGLK#20, the R5F565NEDFP#30 reduces I/O and connectivity for compact control nodes, while the R5F566TEBGLK#20 trades networking capability for deterministic motor control-making R5F565N4BGLK#20 uniquely balanced for secure, graphics-enabled, networked edge devices.
Availability
R5F565N4BGLK#20 is available at Aetrix Electronics and suitable for industrial HMIs, secure IoT gateways, networked energy meters, and medical data loggers requiring stable component supply across multi-year production cycles.
Supply support for R5F565N4BGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX65N Group-including R5F565N4BGLK#20-is designed for industrial and building automation systems requiring robust real-time performance, functional safety compliance (IEC60730), and integrated connectivity including Ethernet, CAN, and SDIO.
FAQ
What is the maximum operating frequency and CPU performance of the R5F565N4BGLK#20?
The R5F565N4BGLK#20 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance using the RXv2 CPU core. Its single-precision IEEE-754 floating-point unit (FPU) and dual multiply-accumulate units enable efficient math-intensive tasks such as motor control algorithms and real-time signal processing. This performance level is sustained across the full industrial temperature range (–40°C to +105°C) with no derating.
Does the R5F565N4BGLK#20 support secure firmware updates?
Yes, the R5F565N4BGLK#20 supports secure firmware updates via its dual-bank flash architecture and Trusted Secure IP (TSIP). The dual-bank design allows background programming of one bank while executing from the other-enabling zero-downtime updates. TSIP provides hardware-accelerated AES-128/192/256 encryption and secure key storage, protecting firmware images during download and storage. Additionally, the Memory Protection Unit (MPU) isolates update routines from application code.
What display interfaces does the R5F565N4BGLK#20 integrate for HMI applications?
The R5F565N4BGLK#20 integrates a Graphic-LCD Controller (GLCDC) and 2D Drawing Engine (DRW2D) supporting up to three overlay planes (background, graphic 1, graphic 2), 32-/16-bpp pixel formats, and CLUT-based color lookup tables. It drives parallel RGB/TTL displays up to XGA (1024×768) resolution and accelerates vector drawing, bit blitting, rotation, and stretching-all without CPU intervention. This eliminates the need for external display controllers in cost-sensitive industrial HMI designs.
Can the R5F565N4BGLK#20 interface directly with an Ethernet PHY?
Yes, the R5F565N4BGLK#20 includes a fully integrated Ethernet MAC supporting both MII and RMII physical interfaces. It provides dedicated pins (ETH_MDC/ETH_MDIO, RMII_RXD0/RXD1/TXD0/TXD1/TXEN/REF_CLK) for direct connection to standard Ethernet PHYs such as the LAN8720A or DP83848. The on-chip EDMAC controller handles descriptor-based DMA transfers, reducing CPU overhead. The MAC complies with IEEE 802.3 and supports 10/100 Mbps full/half-duplex, flow control (802.3x), and wake-on-LAN.
What safety certifications and features does the R5F565N4BGLK#20 support for industrial use?
The R5F565N4BGLK#20 is designed to support IEC60730 Class B compliance with built-in safety features including oscillation-stop detection, CRC calculator (8/32-bit), independent watchdog timer (IWDT) with configurable window function, self-diagnostic A/D converter, and register write protection. Its Memory Protection Unit (MPU) enforces memory access boundaries, and the Trusted Memory (TM) function prevents unauthorized readout of protected code flash regions. These features collectively enable certified functional safety implementations in industrial control and building automation.
R5F565N4BGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N4BGLK#20 FAQ
1.How can I place an order for R5F565N4BGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N4BGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N4BGLK#20 reliable?
The price and inventory of R5F565N4BGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N4BGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F565N4BGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N4BGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N4BGLK#20?
R5F565N4BGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N4BGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N4BGLK#20?
For technical support, including R5F565N4BGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N4BGLK#20 requirements.
6.How does Aetrix verify that R5F565N4BGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F565N4BGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N4BGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F565N4BGLK#20?
All R5F565N4BGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N4BGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N4BGLK#20 part is unused and in its original packaging.
Return procedure for R5F565N4BGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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