Renesas R5F565N4EGFB#10
- Part No.:
- R5F565N4EGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F565N4EGFB#10.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,993
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Product details
Overview
R5F565N4EGFB#10 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, Ethernet MAC, CAN 2.0B, SD host/slave, QSPI, and hardware AES-128/192/256 encryption - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F565N4EGFB#10 datasheet, R5F565N4EGFB#10 pinout, R5F565N4EGFB#10 application, or R5F565N4EGFB#10 equivalent, key selection criteria include dual-bank flash for safe firmware updates, 136 GPIOs with 5-V tolerance, IEEE 802.3-compliant 10/100 Mbps Ethernet with RMII/MII, and IEC60730 safety support including CRC, IWDT, and self-diagnostic A/D.
Technical Context
The R5F565N4EGFB#10 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a single-precision IEEE-754 FPU, two MAC units, and a 32-bit multiplier executing in one cycle - all operating at up to 120 MHz with 240 DMIPS throughput.
Its clock system combines external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL for flexible domain partitioning: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/EDMAC/GLCDC, and PCLKB up to 60 MHz for most peripherals including S12AD units and TMR timers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe firmware swap |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| ADC | Two 12-bit units: S12AD0 (8 channels) and S12AD1 (21 channels), 0.48 µs conversion time per channel |
| Communication | Ethernet MAC (10/100 Mbps, MII/RMII), CAN 2.0B (2 channels, 32 mailboxes each), USB 2.0 FS host/function, SDHI/SDSI, QSPI, 3× RSPI, 3× RIIC, 13× SCI |
| Security | AES-128/192/256 engine + Trusted Secure IP (TSIP) for key management and encrypted boot |
| Package | LFBGA-176 (PLQP0176KB-A), 24 × 24 mm, 0.5-mm pitch, 136 GPIOs with 5-V tolerance |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm ball pitch, RoHS-compliant, rated for –40°C to +105°C (G-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for ADC/DAC operation |
| XTAL / EXTAL | Main clock oscillator terminals | Supports 8–24 MHz crystal for precise timing; required for Ethernet PHY synchronization and RTC accuracy |
| MDIO / MDC | PHY management interface | Enables IEEE 802.3-compliant register access to external Ethernet PHY without MCU intervention |
| ETXD0–ETXD3 / ETXEN / ETXER | Ethernet transmit signals | 4-bit parallel transmit bus + enable/error lines for MII mode; supports 100 Mbps full-duplex operation |
| ERXD0–ERXD3 / ERXDV / ERXER | Ethernet receive signals | 4-bit parallel receive bus + valid/error lines for MII; RMII mode uses reduced 2-bit data + REF_CLK |
| VBATT | Battery backup supply | Provides power to RTC and standby RAM during main VCC loss - enables persistent timekeeping and state retention |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash memory | Enables seamless firmware updates via bank swap without halting real-time execution or losing connectivity |
| IEC60730 Class B support | Includes oscillation-stop detection, CRC calculator (CRCA), IWDT windowing, and A/D self-diagnostic for safety-critical certification |
| Graphics subsystem | Integrated GLCDC + DRW2D engine supports 3-plane overlay, 32-bit pixel rendering, and hardware-accelerated bit blitting for HMI display offload |
| CMOS camera interface | PDC unit captures parallel 8-bit video streams with horizontal/vertical sync - eliminates need for external image processor in vision edge nodes |
| Secure boot & key storage | Trusted Memory (TM) protects boot code from read-out; TSIP provides tamper-resistant AES key generation and storage |
Applications
| Industrial HMI Controller | Smart Gateway Device |
|---|---|
Use Scenario: Touch-enabled factory floor panel running real-time process visualization and local control logic. IC Role / Device Role / Timing Role: Main application processor managing GLCDC-driven LCD, DRW2D-accelerated UI rendering, and EtherCAT-over-Ethernet communication. Use Value: 640 KB SRAM buffers frame data for 800×480 displays; dual-bank flash allows OTA updates without interrupting HMI responsiveness. | Use Scenario: Field-deployed protocol translator aggregating Modbus RTU, CAN bus, and BLE sensor data into MQTT over Ethernet. IC Role / Device Role / Timing Role: Central protocol bridge with concurrent Ethernet MAC, dual CAN channels, and hardware AES for TLS offload. Use Value: Integrated SDHI stores configuration logs; TSIP accelerates TLS handshake by >4× vs software-only crypto, reducing latency under load. |
| Secure IoT Edge Node | Networked Power Monitor |
Use Scenario: Tamper-resistant energy meter with encrypted firmware, remote firmware validation, and secure cloud telemetry. IC Role / Device Role / Timing Role: Root-of-trust controller executing signed firmware, performing AES-GCM encryption on sensor data before transmission. Use Value: TM-protected boot ensures only authenticated code runs; TSIP prevents key extraction even under physical attack - meets IEC 62443-3-3 SL2. | Use Scenario: DIN-rail mounted power quality analyzer capturing voltage/current waveforms via 12-bit ADC and reporting harmonics over Ethernet. IC Role / Device Role / Timing Role: High-precision measurement engine synchronizing S12AD1 (21-channel) sampling to PCLKD at 60 MHz for sub-microsecond timestamping. Use Value: Dual ADC units allow simultaneous acquisition of 8 analog inputs (unit 0) and 21 high-resolution channels (unit 1); 0.48 µs conversion enables 2 MSPS aggregate sampling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | LQFP-144 package (20×20 mm), 111 GPIOs, 1.5 MB flash, 256 KB SRAM | Lacks Ethernet MAC and SD interfaces; no GLCDC/DRW2D graphics engine | Select when board space constraints favor LQFP and Ethernet/HMI features are unnecessary |
| R5F566TEHDFP#30 | RX66T Group, 160 MHz, 2 MB flash, 384 KB SRAM, enhanced PWM (3-phase inverter control), no Ethernet or SD | Optimized for motor control with MTU3 complementary PWM and dead-time compensation; no networking peripherals | Choose for servo drives or inverters requiring real-time PWM precision over connectivity |
Compared with R5F565N4EGFB#10, the R5F565NEDFP#30 reduces footprint and cost but sacrifices Ethernet, SD, and graphics capabilities; the R5F566TEHDFP#30 trades networking for deterministic motor control features - neither offers pin compatibility or identical peripheral sets.
Availability
R5F565N4EGFB#10 is available at Aetrix Electronics and suitable for industrial HMI, smart gateway, and secure IoT edge applications requiring stable component supply, long-term lifecycle assurance, and automotive-grade temperature resilience (–40°C to +105°C).
Supply support for R5F565N4EGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX65N Group - including R5F565N4EGFB#10 - was designed for secure, connected industrial edge devices requiring real-time processing, rich human-machine interaction, and functional safety compliance (IEC60730).
FAQ
What is the maximum operating frequency and performance rating of the R5F565N4EGFB#10?
The R5F565N4EGFB#10 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS (Dhrystone MIPS) performance. Its RXv2 CPU core includes a single-precision IEEE-754 FPU, two MAC units, and a 32-bit multiplier executing in one cycle - enabling deterministic real-time computation for industrial control loops and signal processing tasks within the R5F565N4EGFB#10.
Does the R5F565N4EGFB#10 support Ethernet connectivity, and what interface modes are available?
Yes, the R5F565N4EGFB#10 integrates a full IEEE 802.3-compliant Ethernet MAC supporting both 10 Mbps and 100 Mbps speeds in full- and half-duplex modes. It supports MII (Media Independent Interface) and RMII (Reduced MII) physical layer interfaces, with dedicated MDIO/MDC pins for PHY register access and optional Wake-on-LAN functionality - all implemented natively within the R5F565N4EGFB#10 without external PHY logic.
How does the R5F565N4EGFB#10 implement functional safety for IEC60730 compliance?
The R5F565N4EGFB#10 includes multiple hardware features for IEC60730 Class B compliance: oscillation-stop detection, CRC calculator (CRCA) with configurable polynomials, independent watchdog timer (IWDT) with windowing, self-diagnostic A/D converter test modes, and register write protection. These capabilities are documented in the R5F565N4EGFB#10 datasheet and enable certified safety firmware implementation without external monitoring components.
What graphics and display capabilities are integrated into the R5F565N4EGFB#10?
The R5F565N4EGFB#10 integrates a full Graphic-LCD Controller (GLCDC) supporting 3-layer overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) with vector drawing, bit blitting, rotation, and texture mapping. It supports 32-/16-/8-bit pixel formats and CLUT-based color lookups - enabling direct drive of VGA, SVGA, and WVGA panels without external GPU, a key differentiator of the R5F565N4EGFB#10 in HMI applications.
Is the R5F565N4EGFB#10 pin-compatible with other RX65N Group MCUs, and what package does it use?
No, the R5F565N4EGFB#10 uses the PLQP0176KB-A 176-pin LFBGA package (24×24 mm, 0.5-mm pitch) and is not pin-compatible with smaller RX65N variants like the 144-pin LQFP or 100-pin TFLGA packages. Pin counts, peripheral mappings, and power domains differ across RX65N packages - the R5F565N4EGFB#10's 136 GPIOs, Ethernet, SD, and graphics interfaces are exclusive to this 176-pin configuration.
R5F565N4EGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N4EGFB#10 FAQ
1.How can I place an order for R5F565N4EGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N4EGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N4EGFB#10 reliable?
The price and inventory of R5F565N4EGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N4EGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F565N4EGFB#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N4EGFB#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N4EGFB#10?
R5F565N4EGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N4EGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N4EGFB#10?
For technical support, including R5F565N4EGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N4EGFB#10 requirements.
6.How does Aetrix verify that R5F565N4EGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N4EGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N4EGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F565N4EGFB#10?
All R5F565N4EGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N4EGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N4EGFB#10 part is unused and in its original packaging.
Return procedure for R5F565N4EGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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