Renesas R5F565N4FGFP#10
- Part No.:
- R5F565N4FGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N4FGFP#10.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,449
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Product details
Overview
R5F565N4FGFP#10 from Renesas is a 120-MHz 32-bit RXv2 core MCU with on-chip FPU, 240 DMIPS performance, 2-MB code flash (dual-bank), 640-KB SRAM, Ethernet MAC, CAN, SD host/slave, QSPI, and hardware AES/TSIP encryption - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F565N4FGFP#10 datasheet, R5F565N4FGFP#10 pinout, R5F565N4FGFP#10 application, or R5F565N4FGFP#10 equivalent, key selection criteria include its 176-pin LFBGA package, -40°C to +105°C operating range, integrated GLCDC+DRW2D for display control, and dual-bank flash enabling safe firmware updates in field-deployed systems.
Technical Context
The R5F565N4FGFP#10 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, supporting IEEE-754 single-precision floating-point operations and two multiply-accumulate units. Its clock system integrates PLL, HOCO/LOCO oscillators, and independent IWDT-dedicated 120-kHz clock.
It features a hierarchical peripheral clock domain: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/EDMAC/AES/GLCDC/DRW2D, and PCLKB up to 60 MHz for most timers and A/D converters - enabling precise timing isolation across real-time, communication, and graphics subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 Mbytes code flash with dual-bank structure enabling background programming and safe firmware swap |
| RAM | 640 Kbytes SRAM (256 KB main + 384 KB expansion), 8 KB standby RAM with battery backup |
| Operating Temp | -40°C to +105°C (G-version), qualified for extended industrial environments |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch |
| Peripherals | Ethernet MAC + RMII/MII, 2× CAN (ISO 11898-1), SDHI/SDSI/MMCIF, QSPI, GLCDC + DRW2D, PDC |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), MPU with 8 regions, register write protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5-mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for ADC/DAC operation |
| VBATT | Battery backup supply | Provides power to RTC and standby RAM during main supply loss, preserving timekeeping and state |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for high-accuracy system clock generation |
| ETH_MDC / ETH_MDIO | IEEE 802.3 management interface | Enables PHY configuration and status monitoring via SMI without dedicated controller overhead |
| ETXD0–ETXD3 / ERXD0–ERXD3 | Ethernet data bus (RMII/MII) | Configurable for 4-bit RMII (10/100 Mbps) or 8-bit MII; supports full/half-duplex and flow control |
| SD0CMD / SD0CLK / SD0DAT0–3 | SD host interface signals | 1- or 4-bit SD bus supporting SD memory cards and SDIO peripherals at up to 25 MB/s |
| QSPI_IO0–3 / QSPI_CLK / QSPI_SSL | Quad SPI interface | Direct connection to serial NOR/NAND flash with quad I/O mode for fast code/data fetch |
| GLCD_D0–23 / GLCD_HSYNC / VSYNC | Graphic LCD controller outputs | 24-bit parallel RGB interface with programmable timing, supporting TFT panels up to WXGA resolution |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware update: one bank executes while the other is reprogrammed, eliminating system downtime |
| Integrated GLCDC + DRW2D | Hardware-accelerated 2D rendering and multi-layer LCD composition reduce CPU load in HMI applications |
| Trusted Secure IP (TSIP) | On-die cryptographic engine accelerates AES, SHA, RSA, and key management - certified for IEC 62443-3-3 |
| Event Link Controller (ELC) | Hardware interconnect between 83 internal events eliminates CPU polling and ISR latency for time-critical sequences |
| SD host + slave + MMCIF | Single-chip support for SD card storage, SDIO peripheral attachment (e.g., Wi-Fi/BT modules), and eMMC boot media |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor running RTOS, driving 800×480 TFT via GLCDC+DRW2D, managing Ethernet/CAN fieldbus bridging. Use Value: Dual-bank flash allows over-the-air firmware updates without halting machine operation; TSIP secures firmware integrity and encrypted telemetry upload. | Use Scenario: Protocol-agnostic industrial gateway aggregating Modbus RTU, CANopen, and EtherNet/IP traffic into MQTT/HTTPS cloud uplinks. IC Role / Device Role / Timing Role: Central protocol translator with Ethernet MAC, dual CAN, RSPI/QSPI for local storage, and hardware crypto for TLS 1.2 handshake acceleration. Use Value: Integrated SDHI and SDSI enable dual-role storage (local log buffer + removable config card); ELC synchronizes CAN message timestamping with Ethernet packet capture. |
| Networked Building Controller | Medical Data Logger |
Use Scenario: HVAC and lighting controller with BACnet/IP and LonWorks support, local web UI, and scheduled firmware validation. IC Role / Device Role / Timing Role: Real-time scheduler managing 12-bit ADC sampling of temperature/humidity sensors, PWM fan control via MTU3, and secure HTTP server via Ethernet stack. Use Value: 640 KB SRAM hosts full TCP/IP stack + web server + local database; AES/TSIP validates signed firmware images before installation. | Use Scenario: Portable patient monitor recording ECG, SpO₂, and temperature with Bluetooth LE telemetry and local encrypted storage. IC Role / Device Role / Timing Role: Sensor fusion hub interfacing analog front-end via 12-bit S12AD, buffering data in SRAM, encrypting logs using TSIP before writing to SD card. Use Value: Standby RAM preserves last vital sign snapshot during battery swap; 12-bit D/A drives analog calibration references; RTC with battery backup maintains accurate timestamps across power cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 176-pin LFBGA, but 1-MB flash and 256-KB SRAM; no dual-bank flash | Suitable for cost-sensitive designs where firmware update safety is secondary to BOM reduction | Select when application firmware size ≤ 1 MB and background programming is not required |
| R5F566TEADFP#30 | RX66T Group, 144-pin LQFP, 160-MHz CPU, 1-MB flash, no Ethernet or GLCDC; adds motor control timers (MTU3 enhanced) | Targeted at servo/inverter control with encoder feedback and PWM dead-time compensation | Choose for motion control over connectivity - lacks Ethernet, SD, and graphics engines present in R5F565N4FGFP#10 |
Compared with R5F565NEDFP#30, the R5F565N4FGFP#10 provides double flash capacity and dual-bank safety for field-upgradable systems; versus R5F566TEADFP#30, it trades motor-control precision for integrated networking, storage, and display - making it optimal for connected HMI and gateway roles rather than real-time motor drive.
Availability
R5F565N4FGFP#10 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and networked building controllers requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for R5F565N4FGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group - including R5F565N4FGFP#10 - was designed for high-integrity industrial applications demanding integrated connectivity (Ethernet/CAN/SD), graphics capability (GLCDC/DRW2D), and hardware security (TSIP/AES) in a single chip.
FAQ
What is the maximum operating frequency and CPU performance of the R5F565N4FGFP#10?
The R5F565N4FGFP#10 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance using the RXv2 32-bit CPU core. Its single-precision IEEE-754 floating-point unit and dual MAC units enable deterministic real-time computation for industrial control algorithms. This performance level is confirmed in the official Renesas datasheet R01DS0276EJ0240 Rev.2.40.
Does the R5F565N4FGFP#10 support secure firmware updates?
Yes, the R5F565N4FGFP#10 supports secure firmware updates via its dual-bank flash architecture and Trusted Secure IP (TSIP). The dual-bank feature allows one bank to run active firmware while the other is programmed, ensuring zero-downtime updates. TSIP provides hardware-accelerated AES decryption and signature verification, protecting R5F565N4FGFP#10 firmware integrity against tampering during OTA deployment.
What display interfaces does the R5F565N4FGFP#10 integrate?
The R5F565N4FGFP#10 integrates a Graphic-LCD Controller (GLCDC) supporting 24-bit RGB parallel output and a 2D Drawing Engine (DRW2D) for hardware-accelerated bit blitting, vector drawing, and layer composition. It drives TFT panels up to WXGA resolution with programmable timing, and the DRW2D offloads CPU-intensive rendering tasks - critical for responsive HMI in resource-constrained R5F565N4FGFP#10-based systems.
Can the R5F565N4FGFP#10 operate in extended temperature environments?
Yes, the R5F565N4FGFP#10 is rated for operation from –40°C to +105°C (G-version), making it suitable for harsh industrial environments such as factory automation, outdoor gateways, and building management systems. Its thermal design includes on-chip temperature sensing with ±1°C accuracy, and the RTC remains functional under battery backup during main supply interruption - both validated for the full R5F565N4FGFP#10 temperature range.
What communication peripherals are included in the R5F565N4FGFP#10?
The R5F565N4FGFP#10 integrates Ethernet MAC (10/100 Mbps with RMII/MII), dual CAN 2.0B channels (32 mailboxes each), SD host/slave interfaces, QSPI, three RSPI channels, three I²C buses (up to 1 Mbps), and 13 SCI channels with flexible modes (UART, SPI, I²C, LIN). These interfaces enable R5F565N4FGFP#10 to serve as a central connectivity hub in multi-protocol industrial systems without external bridge ICs.
R5F565N4FGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N4FGFP#10 FAQ
1.How can I place an order for R5F565N4FGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N4FGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N4FGFP#10 reliable?
The price and inventory of R5F565N4FGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N4FGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F565N4FGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N4FGFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N4FGFP#10?
R5F565N4FGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N4FGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N4FGFP#10?
For technical support, including R5F565N4FGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N4FGFP#10 requirements.
6.How does Aetrix verify that R5F565N4FGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N4FGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N4FGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F565N4FGFP#10?
All R5F565N4FGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N4FGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N4FGFP#10 part is unused and in its original packaging.
Return procedure for R5F565N4FGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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