My Inquiry
My Account
Renesas R5F565N7AGFB#10
- Part No.:
- R5F565N7AGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F565N7AGFB#10.pdf
- Description:
- IC MCU 32BIT 768KB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,044
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F565N7AGFB#10 from Renesas is a 120-MHz 32-bit RXv2 core MCU with on-chip FPU, 240 DMIPS performance, 2 MB code flash (dual-bank), 640 KB SRAM, Ethernet MAC, CAN 2.0B (2 channels), SD host/slave interfaces, and hardware AES-128/192/256 encryption - deployed in industrial HMI controllers requiring real-time graphics, secure connectivity, and deterministic I/O.
For engineers reviewing the R5F565N7AGFB#10 datasheet, R5F565N7AGFB#10 pinout, R5F565N7AGFB#10 application, or R5F565N7AGFB#10 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C operating range (G-version), integrated GLCDC + DRW2D for embedded GUIs, and dual-bank flash enabling safe firmware updates without runtime interruption.
Technical Context
The R5F565N7AGFB#10 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, supporting little-endian or big-endian data arrangement and ultra-compact variable-length instructions. Its CPU executes single-cycle 32×32-bit multiply and two-cycle divide operations while delivering IEEE-754-compliant single-precision floating-point math at 120 MHz.
Peripherals are clocked across four independent domains: ICLK (up to 120 MHz for CPU), PCLKA (up to 120 MHz for ETHERC, GLCDC, DRW2D), PCLKB (up to 60 MHz for most timers and communication modules), and PCLKC/PCLKD (up to 60 MHz for S12AD units). This domain separation enables precise power/performance tuning and concurrent high-speed Ethernet and graphics rendering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe firmware swap |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| Operating Temp | -40°C to +105°C (G-version), qualified for extended industrial environments |
| Package | 176-pin LFBGA (PLQP0176KB-A), 24 × 24 mm, 0.5-mm pitch, 136 general-purpose I/O pins |
| Security | Hardware AES engine (128/192/256-bit keys) + Trusted Secure IP (TSIP) for cryptographic key management |
| Graphics | Integrated Graphic-LCD controller (GLCDC) and 2D drawing engine (DRW2D) supporting 3-plane overlay and vector/bit-blit acceleration |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array, 24 mm × 24 mm, 0.5-mm ball pitch, 136 configurable I/O pins with 5-V tolerance on 19 pins, open-drain capability, and programmable pull-up resistors.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for ADC/DAC operation |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system timing and Ethernet PHY synchronization |
| ETH_MDC / ETH_MDIO | IEEE 802.3 MII/RMII management interface | Enables configuration and status monitoring of external Ethernet PHY without CPU intervention |
| SD0_CMD / SD0_CLK / SD0_DAT[0:3] | SD host interface signals | Direct 4-bit SD bus interface compliant with SD Physical Layer Spec v3.01 (no DDR support) |
| CAN0_TX / CAN0_RX / CAN1_TX / CAN1_RX | CAN transceiver I/O | Dedicated differential pairs per channel, ISO 11898-1 compliant, each with 32 configurable mailboxes |
| GLCD_D[0:23] / GLCD_HSYNC / GLCD_VSYNC | Graphic LCD parallel interface | 24-bit RGB data bus + sync signals supporting TFT panels up to WXGA resolution |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash memory | Enables seamless firmware update: one bank executes while the other is reprogrammed, eliminating runtime interruption |
| Integrated GLCDC + DRW2D | Offloads GUI rendering from CPU - supports 3-layer composition, alpha blending, and hardware-accelerated 2D primitives |
| Hardware AES + TSIP | Secure boot and OTA update integrity: cryptographic operations executed in tamper-resistant hardware, not software |
| Event Link Controller (ELC) | Eliminates CPU polling: 83 internal event signals (e.g., timer overflow, ADC completion) trigger peripheral actions autonomously |
| SD host + SD slave + MMCIF | Unified storage interface: supports SD memory cards, SDIO peripherals (Wi-Fi/BT modules), and eMMC in same design |
Applications
| Industrial HMI Panel | Secure Gateway Controller |
|---|---|
Use Scenario: Embedded touchscreen panel in factory automation systems with real-time alarm display, recipe management, and local data logging. IC Role / Device Role / Timing Role: Primary application processor running RTOS, driving 800×480 TFT via GLCDC, executing AES-encrypted Modbus TCP over Ethernet. Use Value: DRW2D accelerates button animations and chart redraws; dual-bank flash allows field firmware updates without halting machine control logic. | Use Scenario: Edge gateway aggregating CAN bus data from PLCs and sensors, encrypting payloads, and forwarding to cloud via Ethernet. IC Role / Device Role / Timing Role: Central protocol translator with simultaneous CAN 2.0B (2 channels), Ethernet MAC, and hardware AES crypto acceleration. Use Value: On-chip TSIP securely stores device identity keys; ELC synchronizes CAN message receipt with AES encryption start - no CPU cycles wasted on handshaking. |
| Medical Device UI | Smart Energy Meter |
Use Scenario: Portable diagnostic instrument with color LCD, touch input, battery-backed RTC, and USB host for printer/dongle connectivity. IC Role / Device Role / Timing Role: System-on-chip managing display, touch controller interface (via PDC), USB FS host, and temperature-compensated RTC. Use Value: Integrated temperature sensor feeds calibration data to S12AD unit 1; standby RAM preserves UI state during low-power sleep modes. | Use Scenario: DIN-rail mounted electricity meter with LCD, IR/RF communication, tamper detection, and secure firmware updates. IC Role / Device Role / Timing Role: Safety-certified controller implementing IEC 60730 Class B diagnostics, CRC validation, and watchdog supervision. Use Value: Built-in CRCA module validates firmware images; IWDT with window function prevents malicious or runaway code from disabling safety checks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 144-pin LQFP package (PLQP0144KA-B), 1.5 MB flash, 256 KB SRAM, -40°C to +85°C (D-version) | Lacks SD slave interface and second CAN channel; lower I/O count (111 pins) and reduced graphics bandwidth | Select when board space permits LQFP, thermal budget limits operation to 85°C, and dual CAN/SD slave is unnecessary. |
| R5F566TEADFP#30 | RX66T Group, 144-pin LQFP, 160 MHz CPU, 1.5 MB flash, 384 KB SRAM, enhanced PWM (3-phase inverter control), no Ethernet or GLCDC | Optimized for motor control with MTU3-based complementary PWM and dead-time compensation; no graphics or networking peripherals | Select for servo drives or inverters where real-time motor timing dominates over HMI/cloud connectivity requirements. |
Compared with R5F565N7AGFB#10, the R5F565NEDFP#30 trades package size and temperature grade for reduced integration (no SD slave, single CAN), while the R5F566TEADFP#30 abandons Ethernet/GLCDC entirely to deliver higher PWM precision and CPU speed for motion control - neither is pin-compatible, and both require PCB redesign.
Availability
R5F565N7AGFB#10 is available at Aetrix Electronics and suitable for industrial HMI panels, secure gateways, medical UIs, and smart energy meters requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability under extended temperature stress.
Supply support for R5F565N7AGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX65N Group - including R5F565N7AGFB#10 - was designed for high-integration industrial human-machine interfaces requiring embedded graphics, secure connectivity, and functional safety compliance (IEC 60730).
FAQ
What is the maximum operating frequency and CPU performance of the R5F565N7AGFB#10?
The R5F565N7AGFB#10 operates at a maximum frequency of 120 MHz using the RXv2 32-bit CPU core and delivers 240 DMIPS of processing performance. Its on-chip single-precision IEEE-754 floating-point unit (FPU) enables efficient mathematical computation for real-time control and signal processing tasks within the R5F565N7AGFB#10.
Does the R5F565N7AGFB#10 support secure firmware updates?
Yes, the R5F565N7AGFB#10 supports secure firmware updates via its dual-bank flash architecture and Trusted Secure IP (TSIP). The dual-bank feature allows background programming of one bank while executing from the other, ensuring uninterrupted operation. TSIP provides hardware-accelerated AES encryption and secure key storage, protecting firmware images validated before execution on the R5F565N7AGFB#10.
What graphics capabilities does the R5F565N7AGFB#10 integrate?
The R5F565N7AGFB#10 integrates a Graphic-LCD Controller (GLCDC) supporting 24-bit RGB output and a 2D Drawing Engine (DRW2D) capable of vector drawing (lines, triangles, circles) and bit blitting with rotation and scaling. These accelerators offload GUI rendering from the CPU, enabling smooth animation and multi-layer overlays - critical for responsive HMI applications built around the R5F565N7AGFB#10.
Which communication interfaces are available on the R5F565N7AGFB#10 for industrial networking?
The R5F565N7AGFB#10 provides Ethernet MAC (10/100 Mbps, MII/RMII), two CAN 2.0B channels (32 mailboxes each), three RSPI, one QSPI, three I²C, up to 13 SCI channels, SD host/slave, and MMCIF interfaces. This comprehensive set supports industrial protocols like Modbus TCP, CANopen, and fieldbus bridging - all implemented directly on the R5F565N7AGFB#10 without external co-processors.
What is the operating temperature range and package type of the R5F565N7AGFB#10?
The R5F565N7AGFB#10 is rated for -40°C to +105°C operation (G-version) and uses a 176-pin LFBGA package (PLQP0176KB-A) measuring 24 mm × 24 mm with 0.5-mm ball pitch. This package supports 136 general-purpose I/O pins, 19 of which are 5-V tolerant, making the R5F565N7AGFB#10 suitable for harsh industrial environments requiring thermal resilience and robust interfacing.
R5F565N7AGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7AGFB#10 FAQ
1.How can I place an order for R5F565N7AGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7AGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7AGFB#10 reliable?
The price and inventory of R5F565N7AGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7AGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F565N7AGFB#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N7AGFB#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N7AGFB#10?
R5F565N7AGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7AGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7AGFB#10?
For technical support, including R5F565N7AGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7AGFB#10 requirements.
6.How does Aetrix verify that R5F565N7AGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N7AGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7AGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F565N7AGFB#10?
All R5F565N7AGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7AGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7AGFB#10 part is unused and in its original packaging.
Return procedure for R5F565N7AGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N7AGFB#10 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
