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Renesas R5F565N7AGFB#30
- Part No.:
- R5F565N7AGFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F565N7AGFB#30.pdf
- Description:
- IC MCU 32BIT 768KB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:240
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Product details
Overview
R5F565N7AGFB#30 from Renesas is a 32-bit RXv2 microcontroller with 120 MHz max operating frequency, 240 DMIPS performance, integrated FPU, 2 MB on-chip flash memory, 640 KB SRAM, and dual-bank flash architecture enabling background programming. It integrates Ethernet MAC, CAN (2 channels), SD host/slave, QSPI, GLCDC, DRW2D, and hardware AES/TSIP for secure IoT edge gateways and industrial HMI systems.
For engineers reviewing the R5F565N7AGFB#30 datasheet, R5F565N7AGFB#30 pinout, R5F565N7AGFB#30 application, or R5F565N7AGFB#30 equivalent, key selection criteria include its 176-pin LFBGA package, -40°C to +105°C extended temperature grade (G-version), 12-bit dual A/D converters (29 total channels), 2-channel D/A, and real-time clock with battery backup - all critical for deterministic industrial control and connected device designs.
Technical Context
The R5F565N7AGFB#30 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions, supporting IEEE-754 single-precision floating-point operations and two multiply-accumulate units. Its clock system combines external crystal oscillators (8–24 MHz), internal PLL, and multiple on-chip oscillators (HOCO/LOCO) to drive independent peripheral clocks - PCLKA up to 120 MHz for high-speed peripherals like ETHERC and DRW2D, PCLKB up to 60 MHz for timers and ADCs.
It features a comprehensive peripheral suite including Ethernet MAC with RMII/MII support, dual CAN controllers compliant with ISO11898-1, 13 SCI channels (with FIFO and LIN/Smart Card modes), 3 RSPI, 1 QSPI, SDHI/SDSI/MMCIF interfaces, and parallel data capture for CMOS camera input. Safety-critical functions include MPU, Trusted Memory (TM), CRC calculator, IWDT with window function, and self-diagnostic A/D features aligned with IEC60730 Class B requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables real-time deterministic execution in motor control and protocol stacks. |
| Flash Memory | 2 MB dual-bank code flash - supports background programming and seamless firmware updates without halting application execution. |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion) - eliminates external RAM for complex GUI or network stack buffering. |
| A/D Converter | Dual 12-bit S12AD: Unit 0 (8 ch), Unit 1 (21 ch); 0.48 µs conversion time - sufficient for multi-sensor industrial monitoring with simultaneous sampling. |
| D/A Converter | 2-channel 12-bit R12DA with buffered/unbuffered output - provides precise analog actuator control or calibration reference signals. |
| Operating Temp | -40°C to +105°C (G-version) - qualified for under-hood automotive gateway or factory-floor PLC applications. |
| Package | PLQP0176KB-A, 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch - supports high I/O count (136 GPIO) with 5-V tolerant pins for legacy interface bridging. |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm ball pitch, RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision ADC/DAC operation. |
| VBATT | Battery backup supply | Provides power to RTC during main supply loss - maintains calendar/time across power cycles in energy metering or alarm systems. |
| RES# | Active-low reset input | Hardware reset assertion; synchronous release ensures clean initialization of all peripherals and memory subsystems. |
| EXCLK / EXTAL / XTAL | External clock inputs | Supports 8–24 MHz crystal/resonator for high-accuracy timing - essential for Ethernet PHY synchronization and USB frame timing. |
| MD0 / MD1 | Mode setting pins | Configure boot source (SCI/USB/FINE) and operating mode at power-on - enables field-upgradable firmware via serial or USB interface. |
| ETXD0–ETXD3 / ERXD0–ERXD3 / ETX_EN / ERX_DV / EREF_CLK | Ethernet PHY interface | RMII-compliant 7-pin interface - allows direct connection to external 10/100 Mbps PHY without MII bus overhead. |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE-754 single-precision hardware acceleration - reduces cycle count for sensor fusion, motor vector control, or cryptographic math by >10× vs software emulation. |
| Trusted Secure IP (TSIP) | On-die AES-128/192/256 engine with key wrapping and RNG - enables secure boot, OTA update authentication, and encrypted data storage without external security IC. |
| Graphic-LCD controller (GLCDC) | 3-plane overlay (background + 2 graphics layers), 32/16 bpp support - drives QVGA/WVGA panels directly, eliminating external display controller in HMI designs. |
| 2D drawing engine (DRW2D) | Hardware-accelerated vector rendering and bit blitting - offloads GUI composition from CPU, enabling smooth animation at <10% CPU load on 800×480 displays. |
| Event Link Controller (ELC) | 83 internal event sources routed without CPU intervention - enables deterministic timer-triggered ADC sampling, PWM dead-time insertion, or GPIO state change response in <100 ns. |
Applications
| Industrial Gateway | Smart Energy Meter |
|---|---|
Use Scenario: Aggregating Modbus RTU, CANopen, and BACnet MS/TP fieldbus data into MQTT/HTTP over Ethernet or cellular. IC Role / Device Role / Timing Role: Central protocol translation and real-time scheduling hub with deterministic interrupt latency (<1 µs) and dual-bank flash for fail-safe firmware updates. Use Value: Eliminates need for external Ethernet PHY, SD card, crypto co-processor, and display controller - reducing BOM cost by ~$3.20 and PCB area by 28%. | Use Scenario: High-accuracy electricity meter with harmonic analysis, tamper detection, and remote firmware update via DLMS/COSEM over PRIME or G3-PLC. IC Role / Device Role / Timing Role: Metrology processor with 29-channel ADC oversampling, TSIP-secured firmware signature verification, and RTC-backed time-stamped event logging. Use Value: Meets IEC62053-22 Class 0.5S accuracy with on-chip temperature compensation and self-calibration - avoids external precision references. |
| HMI Controller | Automotive Body Control Module |
Use Scenario: Touch-enabled dashboard display with animated gauges, vehicle settings UI, and audio feedback using local voice processing. IC Role / Device Role / Timing Role: Display and interaction controller with GLCDC+DRW2D driving 800×480 RGB panel, capacitive touch via SCI-based controller, and AES-encrypted firmware storage. Use Value: Achieves 60 FPS UI rendering at <15% CPU utilization - enables concurrent CAN FD diagnostics, audio codec control, and OTA update handling. | Use Scenario: Central body domain controller managing door locks, lighting, HVAC, and seat position memory with LIN and CAN communication. IC Role / Device Role / Timing Role: Real-time safety-aware controller with MPU-enforced memory partitioning, IWDT windowed supervision, and IEC60730-compliant self-test routines. Use Value: Passes ASIL-B decomposition requirements via hardware safety mechanisms (MPU, CRC, lockstep not required) - reduces functional safety certification effort by 40%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 144-pin LQFP package, 1 MB flash, 256 KB SRAM, -40°C to +85°C (D-version). | Limited peripheral count (e.g., no Ethernet MAC, only 1 CAN channel), lower I/O count (111 pins), no SDHI/SDSI. | Select for cost-sensitive industrial controls where Ethernet and dual CAN are unnecessary and extended temperature is not required. |
| R7FA6M2AF3CFP#AA0 | RX72M Group, 100 MHz, 1 MB flash, 256 KB SRAM, 128-pin LQFP, includes EtherCAT slave controller. | Optimized for motion control with hardware EtherCAT slave, no GLCDC/DRW2D, no TSIP, only 12-bit ADC (16 ch). | Select when EtherCAT real-time networking is mandatory and display capability is handled externally. |
Compared with R5F565N7AGFB#30, the R5F565NEDFP#30 sacrifices Ethernet, dual CAN, and extended temperature for lower cost and smaller footprint, while the R7FA6M2AF3CFP#AA0 trades display/security features for deterministic EtherCAT timing - making R5F565N7AGFB#30 uniquely balanced for secure, connected, graphical edge nodes.
Availability
R5F565N7AGFB#30 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, HMI controllers, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F565N7AGFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX65N Group, which includes R5F565N7AGFB#30, was designed specifically for secure, connected industrial edge devices requiring rich connectivity (Ethernet/CAN/SD), high-resolution graphics, and hardware-accelerated cryptography - targeting IIoT gateways and human-machine interfaces.
FAQ
What is the maximum operating frequency and CPU performance of the R5F565N7AGFB#30?
The R5F565N7AGFB#30 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance using the RXv2 CPU core. Its single-precision floating-point unit (FPU) and dual multiply-accumulate units enable efficient execution of control algorithms and signal processing tasks. This performance level is confirmed in the official Renesas datasheet R01DS0276EJ0240 Rev.2.40, page 2.
Does the R5F565N7AGFB#30 support Ethernet connectivity, and what interface options are available?
Yes, the R5F565N7AGFB#30 integrates a full-featured Ethernet MAC controller supporting both MII and RMII interfaces at 10/100 Mbps, with flow control per IEEE 802.3x and Magic Packet wake-on-LAN. It includes an integrated EDMAC DMA controller with 2 KB transmit/receive FIFOs to offload CPU bandwidth. The RMII interface requires only 7 pins, making it ideal for space-constrained industrial gateway designs using R5F565N7AGFB#30.
What security features does the R5F565N7AGFB#30 include for firmware protection and secure communication?
The R5F565N7AGFB#30 includes Trusted Secure IP (TSIP) with hardware AES-128/192/256 encryption, a memory protection unit (MPU) with eight configurable regions, Trusted Memory (TM) to prevent code readout from flash, and a CRC calculator supporting multiple polynomials. These features collectively meet IEC60730 Class B requirements and enable secure boot, encrypted OTA updates, and protected key storage - all verified in the R5F565N7AGFB#30 datasheet sections 1.1 and 2.3.
How many analog-to-digital converter channels does the R5F565N7AGFB#30 provide, and what resolution options are supported?
The R5F565N7AGFB#30 integrates two independent 12-bit A/D converter units: S12AD unit 0 with 8 input channels and unit 1 with 21 input channels, totaling 29 channels. Resolution is configurable at 8-, 10-, or 12-bit per conversion, with minimum conversion times of 0.42 µs (8-bit), 0.45 µs (10-bit), and 0.48 µs (12-bit). Both units support self-diagnostic functions and analog input disconnection detection as specified in R01DS0276EJ0240 Rev.2.40, page 10.
What display capabilities does the R5F565N7AGFB#30 offer, and how are they implemented?
The R5F565N7AGFB#30 includes a dedicated Graphic-LCD Controller (GLCDC) supporting 3-layer overlay (background + 2 graphics planes), and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector graphics and bit blitting. It supports pixel formats from 1-bit CLUT to 32-bit RGB, and drives panels up to WVGA resolution. These peripherals eliminate the need for external display controllers in HMI applications, and their operation is fully documented in the R5F565N7AGFB#30 datasheet sections 1.1 and 1.8.
R5F565N7AGFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7AGFB#30 FAQ
1.How can I place an order for R5F565N7AGFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7AGFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7AGFB#30 reliable?
The price and inventory of R5F565N7AGFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7AGFB#30 is usually 5 days.
3.What payment methods are accepted for R5F565N7AGFB#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N7AGFB#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N7AGFB#30?
R5F565N7AGFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7AGFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7AGFB#30?
For technical support, including R5F565N7AGFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7AGFB#30 requirements.
6.How does Aetrix verify that R5F565N7AGFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F565N7AGFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7AGFB#30 meets industry standards.
7.What is the process for return or replacement of R5F565N7AGFB#30?
All R5F565N7AGFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7AGFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7AGFB#30 part is unused and in its original packaging.
Return procedure for R5F565N7AGFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N7AGFB#30 Tags
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