Renesas R5F565N7BGFB#10
- Part No.:
- R5F565N7BGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F565N7BGFB#10.pdf
- Description:
- IC MCU 32BIT 768KB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,006
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Product details
Overview
R5F565N7BGFB#10 from Renesas is a 120-MHz 32-bit RXv2 core MCU with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, GLCDC, DRW2D, and TSIP encryption. It targets industrial HMI, networked gateway, and secure edge node applications requiring real-time control, graphics rendering, and connectivity.
For engineers reviewing the R5F565N7BGFB#10 datasheet, R5F565N7BGFB#10 pinout, R5F565N7BGFB#10 application, or R5F565N7BGFB#10 equivalent, this page delivers verified technical context, package mapping to PLQP0176KB-A (176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch), confirmed peripheral clock domains (ICLK up to 120 MHz, PCLKA up to 120 MHz, PCLKB up to 60 MHz), and validated alternative selection guidance for functional migration paths.
Technical Context
The R5F565N7BGFB#10 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code. It integrates dual-bank flash supporting background programming and bank-swapping at runtime, alongside 640 KB of zero-wait-state SRAM partitioned into 256 KB main RAM and 384 KB expansion RAM.
Peripheral clocking is segmented: ICLK drives the CPU at up to 120 MHz; PCLKA synchronizes high-bandwidth modules (ETHERC, EDMAC, AES, GLCDC, DRW2D) also at up to 120 MHz; PCLKB governs lower-speed peripherals (TMR, CMT, IWDT, S12AD unit 0) at up to 60 MHz; PCLKC/D drive A/D converters independently at up to 60 MHz. The device supports IEC60730 safety compliance via CRCA, self-diagnostic A/D, oscillation-stop detection, and register write protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS, IEEE-754 FPU, MPU support |
| Memory | 2 MB dual-bank code flash (no-wait ≤50 MHz), 32 KB data flash (100k erase cycles), 640 KB SRAM (zero-wait) |
| Connectivity | Ethernet MAC + RMII/MII, 2× CAN (ISO11898-1, 32 mailboxes/channel), 3× RSPI, 1× QSPI, 3× RIIC (1 Mbps), 13× SCI |
| Graphics & Media | GLCDC (3-plane overlay), DRW2D (vector/bit-blit), PDC (CMOS camera interface), SDHI/SDSI/MMCIF (25–30 MB/s) |
| Analog | Two 12-bit S12AD units (8+21 ch), 2× R12DA (12-bit buffered/unbuffered), on-die temperature sensor (±1°C) |
| Security & Safety | TSIP encryption (AES-128/192/256), Trusted Memory (TM), CRCA (8/32-bit), register write protection, IEC60730 features |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm body, 0.5 mm ball pitch, lead-free, RoHS-compliant, rated for –40°C to +105°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/digital (VCC), analog unit 0 (AVCC0), analog unit 1 (AVCC1); all require 2.7–3.6 V with decoupling |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin cell or backup source |
| RES# | Active-low reset input | Hardware reset assertion; internal pull-up; compatible with open-drain drivers |
| CLKIN / CLKOUT | External crystal oscillator interface | Supports 8–24 MHz crystal; CLKOUT provides feedback for oscillator stability monitoring |
| ETH_MDC / ETH_MDIO | IEEE 802.3 management interface | Provides MDIO serial bus and MDC clock for PHY configuration and status polling |
| ETH_TXD0–3 / ETH_RXD0–3 | Ethernet physical layer data | 4-bit transmit/receive data bus for RMII mode; requires controlled impedance routing |
| USB_DP / USB_DM | Full-speed USB 2.0 differential pair | Integrated transceiver; no external termination required; supports host/function/OTG |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); includes command, clock, and bidirectional data lines |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates with zero downtime: one bank executes while the other is reprogrammed |
| PCLKA-synchronized high-speed peripherals | Allows Ethernet MAC, GLCDC, and DRW2D to operate concurrently at full 120 MHz without CPU bottleneck |
| Event Link Controller (ELC) | Eliminates CPU intervention by directly chaining 83 internal event sources (e.g., timer overflow → A/D trigger → DMA transfer) |
| Trusted Secure IP (TSIP) | Hardware-accelerated AES encryption/decryption with key wrapping and secure key storage in tamper-resistant memory |
| Graphic-LCD controller + 2D engine | Offloads GUI rendering: GLCDC handles pixel compositing; DRW2D accelerates vector drawing and bit-blit operations |
Applications
| Industrial HMI Panel | Secure IoT Gateway |
|---|---|
Use Scenario: Touch-enabled factory display with real-time process visualization, alarm logging, and local control. IC Role / Device Role / Timing Role: Primary application processor managing GLCDC-driven TFT display, DRW2D-accelerated UI rendering, and Ethernet/SDHI-based data logging. Use Value: 640 KB SRAM enables double-buffered frame buffers; dual-bank flash allows over-the-air firmware updates without interrupting HMI operation. | Use Scenario: Edge gateway aggregating Modbus, CAN, and sensor data, then forwarding via Ethernet/USB to cloud infrastructure. IC Role / Device Role / Timing Role: Central protocol translator and security enforcer, using TSIP for encrypted TLS handshakes and CAN/Ethernet DMA for zero-copy packet forwarding. Use Value: PCLKA-synchronized EDMAC and ETHERC enable 100 Mbps line-rate packet processing; 2 MB flash stores multiple protocol stacks and certificate bundles. |
| Networked Medical Device | Smart Energy Meter |
Use Scenario: Portable diagnostic instrument with LCD display, USB host for printer/storage, and Ethernet for PACS integration. IC Role / Device Role / Timing Role: Real-time controller handling A/D sampling (ECG/SpO₂), GLCDC display output, and USB/SDHI mass storage interfacing. Use Value: On-die temperature sensor and self-diagnostic A/D meet IEC60601-1 Class B requirements; TSIP secures patient data before transmission. | Use Scenario: DIN-rail mounted meter with LCD, optical port, RS485, and Ethernet for AMI communication and firmware updates. IC Role / Device Role / Timing Role: System-on-chip managing metrology A/D conversion, RTC time-stamping, secure firmware validation, and dual-interface communication. Use Value: Dual-bank flash enables fail-safe field upgrades; RTC with battery backup maintains accurate billing timestamps during mains outage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDDFB#30 | Same RX65N Group, identical 120 MHz RXv2 core and peripheral set, but 1 MB code flash and 256 KB SRAM; PLQP0144KA-B (144-pin LFBGA, 20 × 20 mm) | Lower memory capacity and smaller package reduce BOM cost and PCB area; insufficient for full GLCDC+DRW2D framebuffer use cases | Select when application fits within 1 MB flash and does not require >256 KB contiguous RAM for graphics rendering |
| R5F566TEBDFB#30 | RX66T Group part: higher 160 MHz CPU, enhanced MTU3 timers for motor control, no GLCDC/DRW2D, no TSIP, 1.5 MB flash, 384 KB SRAM | Optimized for real-time motor control (inverters, servo drives); lacks graphics and cryptographic acceleration present in R5F565N7BGFB#10 | Select for motion-control systems needing deterministic PWM timing and encoder interfaces, not for HMI or secure gateway roles |
Compared with R5F565N7BGFB#10, the R5F565NEDDFB#30 offers reduced memory and footprint for cost-sensitive non-graphics applications, while the R5F566TEBDFB#30 trades graphics/security for superior motor-control timing precision-neither is pin-compatible, and both require PCB redesign and firmware adaptation.
Availability
R5F565N7BGFB#10 is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and networked medical devices requiring stable component supply, long-term lifecycle assurance, and automotive-grade temperature resilience (–40°C to +105°C).
Supply support for R5F565N7BGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX65N Group, including R5F565N7BGFB#10, was designed for high-integration embedded applications demanding rich connectivity (Ethernet/CAN/USB/SD), graphics capability (GLCDC/DRW2D), and hardware security (TSIP), targeting next-generation industrial HMIs and secure edge nodes.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565N7BGFB#10?
The R5F565N7BGFB#10 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core features a CISC Harvard architecture with a 5-stage pipeline, variable-length instructions, and support for single-precision IEEE-754 floating-point arithmetic. Its design delivers 240 DMIPS performance and includes an on-chip memory protection unit (MPU) for secure memory access control.
Does the R5F565N7BGFB#10 support dual-bank flash and background programming?
Yes, the R5F565N7BGFB#10 supports dual-bank flash architecture with background programming (BGO). This allows one bank to execute code while the other is being erased or programmed, enabling seamless firmware updates without system interruption. The 2 MB code flash is organized into two independent banks, and startup bank selection can be exchanged dynamically via software control.
What graphics and display capabilities does the R5F565N7BGFB#10 provide?
The R5F565N7BGFB#10 integrates a Graphic-LCD Controller (GLCDC) supporting 3-plane overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing and bit-blit operations. It supports 32-/16-bpp graphics, CLUT formats, and texture mapping. These features make the R5F565N7BGFB#10 suitable for high-resolution industrial HMIs without requiring external graphics processors.
How does the R5F565N7BGFB#10 implement hardware security for embedded applications?
The R5F565N7BGFB#10 implements hardware security through its Trusted Secure IP (TSIP) module, which provides AES-128/192/256 encryption/decryption, secure key storage, and key wrapping. Additional features include Trusted Memory (TM) to prevent code readout from designated flash regions, CRC calculator (CRCA) for data integrity, register write protection, and IEC60730-compliant self-test functions for A/D and oscillator monitoring.
What is the package type and thermal rating of the R5F565N7BGFB#10?
The R5F565N7BGFB#10 is packaged in the PLQP0176KB-A: a 176-pin Low-Profile Fine-Pitch Ball Grid Array with 24 mm × 24 mm body size and 0.5 mm ball pitch. It is rated for industrial temperature operation from –40°C to +105°C (G-version), making it suitable for harsh environments such as factory automation and outdoor energy infrastructure where thermal reliability is critical.
R5F565N7BGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7BGFB#10 FAQ
1.How can I place an order for R5F565N7BGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7BGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7BGFB#10 reliable?
The price and inventory of R5F565N7BGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7BGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F565N7BGFB#10?
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R5F565N7BGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7BGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7BGFB#10?
For technical support, including R5F565N7BGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7BGFB#10 requirements.
6.How does Aetrix verify that R5F565N7BGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N7BGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7BGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F565N7BGFB#10?
All R5F565N7BGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7BGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7BGFB#10 part is unused and in its original packaging.
Return procedure for R5F565N7BGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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