Renesas R5F565N7BGFP#10
- Part No.:
- R5F565N7BGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N7BGFP#10.pdf
- Description:
- IC MCU 32BIT 768KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,242
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Product details
Overview
R5F565N7BGFP#10 from Renesas is a 32-bit RXv2 microcontroller with 120 MHz max operating frequency, 240 DMIPS performance, single-precision IEEE-754 FPU, 2 MB on-chip code flash memory (dual-bank), and 640 KB SRAM. It integrates Ethernet MAC, CAN 2.0B (2 channels), SD host/slave interfaces, QSPI, GLCDC, DRW2D, and hardware AES-128/192/256 for industrial HMI and networked edge devices.
For engineers reviewing the R5F565N7BGFP#10 datasheet, R5F565N7BGFP#10 pinout, R5F565N7BGFP#10 application, or R5F565N7BGFP#10 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C G-grade temperature range, integrated 12-bit dual A/D converters (29 total channels), 2-channel 12-bit D/A, and IEC60730-compliant safety features including CRCA, IWDT, and register write protection.
Technical Context
The R5F565N7BGFP#10 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code. Its clock system supports external crystal (8–24 MHz) or internal PLL, with independent domain clocks: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/EDMAC/GLCDC/DRW2D, and PCLKB up to 60 MHz for most peripherals including S12AD units.
It features a full-featured memory subsystem: 2 MB dual-bank flash supporting background programming and bank switching, 32 KB data flash rated for 100,000 erase/write cycles, 640 KB SRAM (256 KB main + 384 KB expansion), and 8 KB standby RAM. Peripheral integration includes DMACA (8 channels), EXDMAC (2 channels), DTC (1 channel), and ELC (83 event signals) for deterministic low-CPU-load data movement and timer/event coordination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic control in motor drives and PLCs |
| Flash Memory | 2 MB dual-bank code flash; allows safe firmware updates without halting execution |
| SRAM | 640 KB (256 KB + 384 KB expansion); supports large frame buffers for GLCDC/DRW2D graphics rendering |
| A/D Converter | Two 12-bit units: S12AD0 (8 ch), S12AD1 (21 ch); 0.48 µs conversion time enables high-speed sensor sampling |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5 mm pitch; suitable for high-density industrial PCB layouts |
| Operating Temperature | -40°C to +105°C (G-version); qualified for under-hood automotive and factory-floor industrial use |
| Security Features | AES-128/192/256 + TSIP; meets IEC60730 Class B requirements for functional safety firmware integrity |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array, 24 mm × 24 mm body, 0.5 mm ball pitch, RoHS-compliant, lead-free solder compatible.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for precision ADC/DAC operation |
| VBATT | Battery backup supply | Provides power to RTC during main VCC dropout; maintains calendar/time across power cycles |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; required for precise Ethernet timing and USB synchronization |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and memory configuration at reset release |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MII/RMII management interface for external Ethernet PHY configuration |
| SD0_D0–SD0_D3 | SD host data bus | 4-bit bidirectional SD bus supporting high-speed mode (25 MB/s); used for SD memory card interfacing |
| QSPI_IO0–QSPI_IO3 | Quad SPI data lines | Supports x1/x2/x4 transfer modes for fast serial flash boot and firmware storage |
| MTU3_TIA0–MTU3_TOB7 | PWM/timer output pins | Drive 3-phase inverter gate drivers with complementary PWM, dead-time insertion, and fault protection via POE3a |
Key Features
| Feature | Design Value |
|---|---|
| Integrated GLCDC + DRW2D | Enables standalone graphic LCD driving with hardware-accelerated 2D drawing (lines, circles, bit blit) and triple-plane overlay without external GPU |
| IEC60730 Safety Support | Includes oscillation-stop detection, CRC calculator (CRCA), IWDT with window function, and register write protection for Class B compliance |
| Dual SD Interfaces | SDHI (host) + SDSI (slave) allow simultaneous SD card read/write and SDIO peripheral control (e.g., Wi-Fi/BT modules) |
| Event Link Controller (ELC) | 83 internal event signals enable direct peripheral-to-peripheral triggering (e.g., TPU → S12AD start), eliminating CPU polling overhead |
| Hardware Crypto Engine | TSIP + AES accelerates secure boot, OTA firmware decryption, and TLS handshake offload in connected industrial devices |
| 136 GPIO with 5V Tolerance | 19 pins support 5V logic input; simplifies interface to legacy sensors, encoders, and industrial I/O without level shifters |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
Use Scenario: Standalone touch-enabled display panel with local logic, real-time data visualization, and SD card logging in factory automation. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving 480×272 RGB LCD via GLCDC, managing touch controller over I2C, and storing logs on SD card via SDHI. Use Value: Integrated DRW2D reduces BOM cost by eliminating external graphics accelerator; dual-bank flash enables seamless field firmware updates without downtime. | Use Scenario: Protocol-convergent gateway aggregating Modbus RTU, CANopen, and EtherNet/IP traffic for cloud telemetry in energy monitoring systems. IC Role / Device Role / Timing Role: Central protocol translator with Ethernet MAC (100 Mbps), dual CAN channels (32 mailboxes each), and multiple SCI/RSPI ports for multi-interface bridging. Use Value: Hardware CRC (CRCA) and IWDT ensure robust packet validation and fail-safe recovery; 120 MHz CPU handles concurrent TCP/IP stack and protocol parsing. |
| Networked Motor Drive | Secure Edge Node |
Use Scenario: Compact servo drive with position feedback, current sensing, and EtherCAT slave interface for collaborative robotics. IC Role / Device Role / Timing Role: Real-time motion controller using MTU3 PWM outputs with dead-time compensation, S12AD for current loop sampling, and ETHERC for EtherCAT communication. Use Value: PCLKA-synchronized 120 MHz timer and ADC enable <1 µs jitter in current-loop control; ELC links TPU triggers directly to S12AD start for deterministic sampling. | Use Scenario: Tamper-resistant IoT sensor node performing local AI inference, encrypted data upload, and secure OTA updates in smart building infrastructure. IC Role / Device Role / Timing Role: Trusted execution environment leveraging TSIP for key management, AES for payload encryption, and secure boot verification before loading application firmware. Use Value: On-chip Trusted Secure IP prevents firmware extraction and cloning; 640 KB SRAM accommodates TensorFlow Lite Micro models and encrypted buffers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEBDFP#30 | Same RX65N Group, 144-pin LFQFP package (PLQP0144KA-B), 1 MB flash, 256 KB SRAM, -40°C to +85°C (D-grade) | Limited peripheral count (e.g., no SDHI, no GLCDC), lower temperature grade; suited for cost-sensitive non-HMI applications | Select when board space permits larger footprint, thermal budget is constrained to 85°C, and graphics/SD functionality is unnecessary. |
| R5F566TEBDFP#30 | RX66T Group, 144-pin LFQFP, 1.5 MB flash, 384 KB SRAM, 160 MHz CPU, enhanced MTU3 with 3-phase PWM and encoder interface | Optimized for motor control with higher PWM resolution and encoder capture; lacks Ethernet MAC and GLCDC | Prefer for servo/inverter designs requiring >120 MHz PWM timing and resolver/encoder support, where networking and display are handled externally. |
Compared with R5F565N7BGFP#10, the R5F565NEBDFP#30 offers reduced integration and lower thermal rating but lower cost and simpler layout, while the R5F566TEBDFP#30 trades Ethernet and graphics for superior motor-control peripherals and higher CPU throughput-making R5F565N7BGFP#10 uniquely balanced for HMI+connectivity+control convergence.
Availability
R5F565N7BGFP#10 is available at Aetrix Electronics and suitable for industrial HMI panels, smart gateways, networked motor drives, and secure edge nodes requiring stable component supply across extended product lifecycles.
Supply support for R5F565N7BGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets, with deep expertise in microcontrollers, analog, and power technologies.
The RX65N Group, which includes R5F565N7BGFP#10, was designed specifically for industrial human-machine interfaces and networked edge controllers requiring integrated graphics, connectivity, security, and real-time control in a single chip.
FAQ
What is the maximum operating frequency and CPU performance of the R5F565N7BGFP#10?
The R5F565N7BGFP#10 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS of processing performance using the RXv2 CPU core. Its single-precision IEEE-754 floating-point unit (FPU) and dual multiply-accumulate units enable efficient signal processing and control algorithms. This performance level supports real-time tasks such as motor control loops, protocol stack handling, and graphics rendering without external co-processors.
Does the R5F565N7BGFP#10 support Ethernet and CAN interfaces simultaneously?
Yes, the R5F565N7BGFP#10 integrates both a 10/100 Mbps Ethernet MAC (ETHERC) with RMII/MII support and two independent CAN 2.0B channels (32 mailboxes per channel). These interfaces operate concurrently using separate clock domains (PCLKA for ETHERC, PCLKB for CAN), enabling applications like industrial gateways that bridge fieldbus networks to IP-based infrastructure without resource contention.
What graphics capabilities does the R5F565N7BGFP#10 provide for HMI applications?
The R5F565N7BGFP#10 includes a dedicated Graphic-LCD Controller (GLCDC) supporting up to 16.7M-color displays and a 2D Drawing Engine (DRW2D) with hardware acceleration for lines, circles, bit blitting, and rotation. It manages three overlay planes and supports 32-/16-bpp graphics formats. These features eliminate the need for external graphics ICs in mid-tier HMIs, reducing BOM cost and PCB complexity while maintaining smooth UI responsiveness.
How does the R5F565N7BGFP#10 meet IEC60730 functional safety requirements?
The R5F565N7BGFP#10 incorporates multiple IEC60730 Class B compliance features: oscillation-stop detection, hardware CRC calculator (CRCA), independent watchdog timer (IWDT) with window function, self-diagnostic A/D converter, and register write protection. These are documented in Renesas' Functional Safety Manual R01UM0572EJ0100 and enable certified safety firmware design without requiring external safety monitors.
What is the flash memory architecture of the R5F565N7BGFP#10, and how does it support firmware updates?
The R5F565N7BGFP#10 features 2 MB of on-chip code flash memory organized in a dual-bank structure, allowing background programming and bank switching. This enables live firmware updates: new code can be written to the inactive bank while the system runs from the active bank, then switched atomically at runtime-ensuring zero-downtime field upgrades essential for industrial equipment with high uptime requirements.
R5F565N7BGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7BGFP#10 FAQ
1.How can I place an order for R5F565N7BGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7BGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7BGFP#10 reliable?
The price and inventory of R5F565N7BGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7BGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F565N7BGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N7BGFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N7BGFP#10?
R5F565N7BGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7BGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7BGFP#10?
For technical support, including R5F565N7BGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7BGFP#10 requirements.
6.How does Aetrix verify that R5F565N7BGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N7BGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7BGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F565N7BGFP#10?
All R5F565N7BGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7BGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7BGFP#10 part is unused and in its original packaging.
Return procedure for R5F565N7BGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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