Renesas R5F565N7BGFP#30
- Part No.:
- R5F565N7BGFP#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N7BGFP#30.pdf
- Description:
- IC MCU 32BIT 768KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:270
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F565N7BGFP#30 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash, 640 KB SRAM, Ethernet MAC, dual CAN channels, SD host/slave interfaces, and hardware AES-128/192/256 encryption - deployed in industrial HMI gateways requiring real-time connectivity, secure firmware updates, and local graphics rendering.
For engineers reviewing the R5F565N7BGFP#30 datasheet, R5F565N7BGFP#30 pinout, R5F565N7BGFP#30 application, or R5F565N7BGFP#30 equivalent, this MCU delivers deterministic real-time control with IEEE-754 floating-point math, IEC60730-compliant safety features, and multi-interface concurrency for edge-node consolidation in factory automation and smart energy systems.
Technical Context
The R5F565N7BGFP#30 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and memory protection unit (MPU) supporting eight configurable regions. It integrates dual-bank flash enabling background programming and safe firmware swapping during runtime.
Clock subsystem includes PLL-based 120 MHz ICLK, independent PCLKA/PCLKB domains (up to 120 MHz / 60 MHz), and dedicated IWDT oscillator. Peripheral clock gating and four low-power modes (sleep, software standby, deep software standby, all-module stop) support <0.19 mA/MHz active power efficiency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 single-precision FPU |
| Memory | 2 MB code flash (dual-bank), 640 KB SRAM (no wait states), 32 KB data flash (100k write cycles) |
| Connectivity | Ethernet MAC (10/100 Mbps), 2× CAN (ISO11898-1), 3× RSPI, 3× I²C (1 Mbps), QSPI, USB 2.0 FS host/function/OTG |
| Analog Peripherals | Two 12-bit ADCs (8 + 21 ch), 2× 12-bit DACs, on-die temperature sensor (±1°C) |
| Graphics & Media | GLCDC (3-plane overlay), DRW2D engine (vector/bitblit), PDC for CMOS camera input |
| Security & Safety | AES-128/192/256, TSIP, MPU, CRC calculator, IEC60730 self-test functions (A/D diag, oscillation detection) |
| Package & Temp | LFBGA-176 (13 × 13 mm, 0.8 mm pitch), –40°C to +105°C (G-version) |
Pinout & Package
LFBGA-176 package (PLBG0176GA-A), 13 × 13 mm body, 0.8 mm ball pitch, 136 general-purpose I/O pins with 5-V tolerance on 19 pins, open-drain capability, and programmable pull-up resistors.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital domains enable noise isolation; AVCC1 powers ADC/DAC/temperature sensor |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator for precise system timing and Ethernet PHY synchronization |
| ETH_MDC / ETH_MDIO | MDIO management interface | Enables run-time PHY register configuration without CPU intervention via EMAC controller |
| CAN0_TX / CAN0_RX | Channel 0 differential CAN bus signals | Direct connection to ISO11898-1 transceiver; supports 1 Mbit/s operation with built-in filtering |
| SD0_CLK / SD0_CMD / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); compatible with SD/SDIO Ver. 3.01 cards |
| GLCD_D0–23 / GLCD_HSYNC / VSYNC | Graphic LCD controller outputs | 24-bit RGB parallel interface with programmable timing; drives TFT panels up to WXGA resolution |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware update with zero downtime: one bank executes while the other is reprogrammed |
| Hardware-accelerated AES engine | Offloads cryptographic operations from CPU; supports ECB/CBC/CTR modes with key lengths up to 256 bits |
| Integrated GLCDC + DRW2D | Eliminates external graphics controller; renders UI elements and overlays in real time using dedicated 2D hardware |
| IEC60730-compliant safety suite | Includes CRC calculator, A/D self-diagnostic, oscillator-stop detection, and register write protection for Class B certification |
| Event Link Controller (ELC) | Hardwires peripheral triggers (e.g., timer overflow → ADC start) without CPU involvement, reducing latency and ISR overhead |
Applications
| Industrial HMI Gateway | Smart Energy Metering Hub |
|---|---|
Use Scenario: Local display, protocol translation (Modbus TCP ↔ CANopen), and secure OTA updates in panel-mounted HMIs. IC Role / Device Role / Timing Role: Central application processor managing Ethernet, dual CAN, SD card logging, and GLCDC-driven 7-inch TFT display. Use Value: Dual-bank flash enables fail-safe firmware upgrades; hardware AES ensures encrypted firmware image integrity. | Use Scenario: Multi-tariff electricity meter with tamper detection, remote reporting, and local LCD display. IC Role / Device Role / Timing Role: Real-time data acquisition hub interfacing with metrology ICs via SPI, storing logs on SD card, and transmitting via Ethernet/Wi-Fi bridge. Use Value: Integrated 12-bit ADCs with self-diagnostic meet IEC62053 accuracy requirements; RTC with battery backup maintains time during mains failure. |
| Factory Automation Edge Node | Building Management System Controller |
Use Scenario: Distributed I/O controller aggregating sensor data, executing motion profiles, and communicating over EtherCAT or PROFINET via external PHY. IC Role / Device Role / Timing Role: Deterministic real-time controller running RTOS with Ethernet MAC, dual CAN, and 16-bit TPU/MTU3 timers for PWM motor control. Use Value: RXv2 core delivers 120 MHz deterministic execution; ELC synchronizes ADC sampling with PWM dead-time generation. | Use Scenario: HVAC controller managing chillers, VAV boxes, and fire alarm integration across BACnet/IP and LonWorks networks. IC Role / Device Role / Timing Role: Protocol gateway with dual Ethernet ports (one for BACnet/IP, one for IT network), SDHI for configuration backup, and CAN for legacy fieldbus bridging. Use Value: Dual Ethernet MAC + integrated PHY support redundant network topologies; 640 KB SRAM buffers large BACnet APDU payloads. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 1.5 MB flash, 256 KB SRAM, LFBGA-176, identical peripherals and pinout | Suitable where firmware size <1.5 MB and lower RAM usage suffices; no GLCDC/DRW2D required | Select when cost-sensitive designs can reduce memory footprint without sacrificing peripheral set |
| R5F566TEBDFP#30 | RX66T Group, 160 MHz, 1 MB flash, 256 KB SRAM, enhanced MTU3 timers, no Ethernet or GLCDC | Optimized for motor control with higher PWM resolution and faster interrupt response; lacks connectivity peripherals | Prefer for servo/inverter applications needing >100 kHz PWM and encoder interface; not suitable as Ethernet/HMI replacement |
Compared with R5F565N7BGFP#30, R5F565NEDFP#30 offers reduced memory at same package and feature set, while R5F566TEBDFP#30 trades connectivity and graphics for superior real-time motor control - making the R5F565N7BGFP#30 uniquely balanced for HMI-rich industrial edge nodes requiring both deterministic control and networked intelligence.
Availability
R5F565N7BGFP#30 is available at Aetrix Electronics and suitable for industrial HMI gateways, smart energy metering hubs, factory automation edge nodes, and building management system controllers requiring stable component supply across extended product lifecycles.
Supply support for R5F565N7BGFP#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.
The RX65N Group targets high-integration industrial applications demanding rich connectivity, graphics, security, and functional safety - designed specifically for HMI, gateway, and edge-control roles where Ethernet, CAN, SD, and cryptography converge.
FAQ
What is the maximum operating frequency and core type of the R5F565N7BGFP#30?
The R5F565N7BGFP#30 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. It achieves 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit. This core supports variable-length instructions, 5-stage pipeline, and memory protection unit (MPU) - all confirmed in the official R01DS0276EJ0240 datasheet Rev.2.40. The R5F565N7BGFP#30 uses the RXv2 architecture exclusively; no ARM or RISC-V cores are present.
Does the R5F565N7BGFP#30 support dual-bank flash for safe firmware updates?
Yes, the R5F565N7BGFP#30 supports dual-bank flash architecture with 2 MB total capacity, enabling background programming and startup bank switching. This allows one bank to execute code while the other is erased or programmed - critical for fail-safe OTA updates. The feature is documented in Section 1.1 (Table 1.1) and Section 2.2.1 of the R01DS0276EJ0240 datasheet. The R5F565N7BGFP#30 implements this natively without external memory or bootloader modifications.
What graphics capabilities does the R5F565N7BGFP#30 provide?
The R5F565N7BGFP#30 integrates a Graphic-LCD Controller (GLCDC) supporting 24-bit RGB output and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing and bit blitting. It handles three-layer plane composition (background, graphic 1, graphic 2) and supports resolutions up to WXGA. These functions are confirmed in Sections 1.1 and 21 of the R01DS0276EJ0240 datasheet. The R5F565N7BGFP#30 requires no external GPU or frame buffer memory for basic HMI rendering.
Which communication interfaces are included in the R5F565N7BGFP#30?
The R5F565N7BGFP#30 includes Ethernet MAC (10/100 Mbps), two CAN 2.0B channels (ISO11898-1), three RSPI, three I²C (up to 1 Mbps), QSPI, USB 2.0 FS host/function/OTG, SD host/slave, and MMCIF interfaces. All are silicon-verified and detailed in Table 1.1 and Section 2.3 of the R01DS0276EJ0240 datasheet. The R5F565N7BGFP#30 does not include PCIe, MIPI, or Bluetooth - only the listed interfaces are physically implemented.
What safety and security features does the R5F565N7BGFP#30 offer for industrial use?
The R5F565N7BGFP#30 provides IEC60730-compliant safety features including CRC calculator (CRCA), A/D converter self-diagnostic, oscillation-stop detection, and register write protection. Security features include AES-128/192/256 hardware engine, Trusted Secure IP (TSIP), and Memory Protection Unit (MPU). These are specified in Sections 1.1, 2.5, and 24 of the R01DS0276EJ0240 datasheet. The R5F565N7BGFP#30 meets Class B requirements out-of-the-box when configured per Renesas application notes.
R5F565N7BGFP#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7BGFP#30 FAQ
1.How can I place an order for R5F565N7BGFP#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7BGFP#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7BGFP#30 reliable?
The price and inventory of R5F565N7BGFP#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7BGFP#30 is usually 5 days.
3.What payment methods are accepted for R5F565N7BGFP#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N7BGFP#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N7BGFP#30?
R5F565N7BGFP#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7BGFP#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7BGFP#30?
For technical support, including R5F565N7BGFP#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7BGFP#30 requirements.
6.How does Aetrix verify that R5F565N7BGFP#30 is sourced from the original manufacturer or authorized distributors?
All R5F565N7BGFP#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7BGFP#30 meets industry standards.
7.What is the process for return or replacement of R5F565N7BGFP#30?
All R5F565N7BGFP#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7BGFP#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7BGFP#30 part is unused and in its original packaging.
Return procedure for R5F565N7BGFP#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N7BGFP#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

