Renesas R5F565N7FDFP#10
- Part No.:
- R5F565N7FDFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N7FDFP#10.pdf
- Description:
- IC MCU 32BIT 768KB FLSH 100LFQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F565N7FDFP#10 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2-MB on-chip code flash (dual-bank), 640-KB SRAM, Ethernet MAC, CAN, SD host/slave, QSPI, and hardware AES/TSIP encryption-designed for industrial HMI, gateway, and secure edge node applications.
For engineers reviewing the R5F565N7FDFP#10 datasheet, R5F565N7FDFP#10 pinout, R5F565N7FDFP#10 application, or R5F565N7FDFP#10 equivalent, key selection criteria include dual-bank flash for safe firmware updates, 136 GPIOs with 5-V tolerance, 120-MHz real-time deterministic execution, and integrated GLCDC+DRW2D for embedded graphics acceleration.
Technical Context
The R5F565N7FDFP#10 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU-enabling deterministic 240 DMIPS at 120 MHz. It integrates dual-bank flash for background programming and bank-swapping during runtime, supporting zero-downtime firmware updates in safety-critical systems.
Its peripheral set includes an Ethernet MAC with RMII/MII support, two CAN 2.0B channels (32 mailboxes each), three RSPI interfaces, one QSPI, three I²C (up to 1 Mbps), and dedicated SDHI/SDSI/MMCIF controllers-all clocked independently via PCLKA/PCLKB up to 120 MHz and 60 MHz respectively, enabling concurrent high-bandwidth data paths without CPU bottlenecks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 Mbytes code flash with dual-bank structure for background programming and safe bank switching |
| SRAM | 640 Kbytes main SRAM + 8 Kbytes standby RAM (retained in deep software standby) |
| ADC/DAC | Two 12-bit A/D converters (8 + 21 channels); two 12-bit D/A converters with buffered/unbuffered output |
| Connectivity | Ethernet MAC (10/100 Mbps, RMII/MII), CAN (2× ISO11898-1), SDHI/SDSI/MMCIF, QSPI, 3× RSPI, 3× I²C (1 Mbps max) |
| Graphics Engine | GLCDC controller + DRW2D 2D drawing engine supporting 32-/16-bpp graphics, bit blitting, rotation, and vector primitives |
| Security | AES-128/192/256 + Trusted Secure IP (TSIP) for key management and cryptographic acceleration |
Pinout & Package
Package: PLQP0176KB-A (176-pin LQFP, 24 × 24 mm, 0.5-mm pitch). Pin count and I/O configuration match RX65N Group specification for 176-pin variants: 136 general-purpose I/O pins with 5-V tolerance on 19 pins, programmable pull-up, open-drain capability, and event-linking support.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital domains enable noise isolation for ADC/DAC operation |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system timing and Ethernet clock derivation |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC for PHY register access and link control |
| TXD0 / RXD0 | SCI0 asynchronous serial interface | Full-duplex UART capable of LIN/UART/Smart Card modes; supports baud rate generation from TMR |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s) per SD Physical Layer Spec v3.01 |
| USB_VBUS / USB_D+ / USB_D− | USB 2.0 FS transceiver interface | Integrated full-speed USB 2.0 host/function/OTG with on-chip transceiver and 2-KB buffer |
| AD00–AD07 / AD10–AD20 | Analog input channels | Unit 0: 8-channel 12-bit ADC; Unit 1: 21-channel 12-bit ADC with self-diagnostic and disconnection detection |
| DA0 / DA1 | Digital-to-analog outputs | 12-bit buffered/unbuffered DACs with voltage range 0.2 V to AVCC1 − 0.2 V |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit | IEEE-754 single-precision FPU enables real-time signal processing and motor control algorithms without software emulation overhead |
| Dual-bank flash memory | Enables seamless firmware updates by executing from one bank while programming the other-critical for industrial gateways requiring zero-downtime maintenance |
| GLCDC + DRW2D | Hardware-accelerated LCD controller and 2D graphics engine reduce CPU load for HMI rendering, supporting 3-layer composition and rotation/scaling |
| Trusted Secure IP (TSIP) | On-chip cryptographic accelerator with key wrapping, secure boot verification, and tamper-resistant key storage-certified for IEC 60730 Class B |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention-e.g., trigger ADC conversion on PWM edge, synchronize timer capture with GPIO change |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Embedded touchscreen display with local logic, sensor fusion, and remote diagnostics in factory automation panels. IC Role / Device Role / Timing Role: Primary application MCU managing GLCDC-driven TFT display, DRW2D-accelerated UI rendering, and real-time EtherCAT/Modbus TCP stack execution. Use Value: Integrated graphics engine eliminates external GPU; dual-bank flash allows over-the-air firmware patching without interrupting HMI operation. | Use Scenario: Protocol-bridging device aggregating CAN, RS485, and BLE sensor data for cloud upload via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Central secure processing node performing TLS encryption, protocol translation, and time-synchronized data logging using RTC and TSIP. Use Value: Hardware AES/TSIP accelerates TLS handshake; Ethernet MAC + SDHI enables local encrypted log storage and fast network upload. |
| Smart Energy Meter | Medical Data Logger |
Use Scenario: DIN-rail mounted meter with harmonic analysis, tamper detection, and secure firmware update capability. IC Role / Device Role / Timing Role: High-precision measurement MCU running FFT-based power quality analysis on ADC samples synchronized to line frequency via ELC-triggered capture. Use Value: 12-bit dual ADC with sample-and-hold and disconnection detection ensures metrology-grade accuracy; IEC 60730 compliance features support safety certification. | Use Scenario: Portable patient monitor recording ECG, SpO₂, and temperature with local display and encrypted export to hospital network. IC Role / Device Role / Timing Role: Safety-certified controller managing analog front-end, DRW2D-rendered waveform display, and AES-encrypted SD card storage. Use Value: Standby RAM preserves critical vitals during battery swap; TSIP enforces HIPAA-compliant data-at-rest encryption on SDHI. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#10 | Same RX65N Group, identical pinout and package (PLQP0176KB-A), but with 1-MB flash and 256-KB SRAM instead of 2-MB/640-KB | Suitable for cost-sensitive designs where dual-bank flash and large SRAM are not required | Select when firmware size < 1 MB and graphics/data buffering needs are reduced |
| R5F566NEDFP#10 | RX66N Group successor: higher 160-MHz CPU, enhanced TSIP-Lite, additional CAN FD channel, same 176-pin LQFP footprint | Targeted at next-gen gateways needing CAN FD, higher crypto throughput, and extended functional safety support | Choose for new designs requiring future-proofing, CAN FD, or ASIL-B readiness |
Compared with R5F565N7FDFP#10, R5F565NEDFP#10 reduces memory capacity while maintaining identical packaging and peripheral compatibility-ideal for scaled-down implementations. R5F566NEDFP#10 offers architectural upgrades including CAN FD and higher clock speed but requires validation of TSIP-Lite integration and updated toolchain support.
Availability
R5F565N7FDFP#10 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateway, and smart energy meter applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F565N7FDFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group-including R5F565N7FDFP#10-is designed for high-performance, secure, and graphics-capable embedded applications demanding real-time responsiveness, functional safety compliance (IEC 60730), and rich connectivity in industrial and medical edge devices.
FAQ
What is the maximum operating frequency and CPU performance of the R5F565N7FDFP#10?
The R5F565N7FDFP#10 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS using the RXv2 CPU core with integrated IEEE-754 single-precision FPU. Its 5-stage pipeline, variable-length instruction set, and on-chip 32-bit multiplier enable deterministic real-time execution critical for industrial control loops and motor drive algorithms. The R5F565N7FDFP#10 sustains this performance across its full temperature range (–40°C to +85°C).
Does the R5F565N7FDFP#10 support dual-bank flash for safe firmware updates?
Yes, the R5F565N7FDFP#10 includes 2 Mbytes of on-chip code flash organized in a dual-bank structure, enabling background programming and bank-swapping during runtime. This allows the R5F565N7FDFP#10 to execute from one bank while reprogramming the other-ensuring zero-downtime firmware updates essential for industrial gateways and medical devices requiring continuous operation.
What graphics capabilities does the R5F565N7FDFP#10 provide for HMI applications?
The R5F565N7FDFP#10 integrates a Graphic-LCD Controller (GLCDC) and a 2D Drawing Engine (DRW2D) supporting 32-/16-bpp graphics, bit blitting, rotation, scaling, and vector primitives. These accelerators offload the CPU from UI rendering tasks, enabling smooth animation and multi-layer composition on TFT displays-making the R5F565N7FDFP#10 ideal for industrial HMIs without external graphics ICs.
How does the R5F565N7FDFP#10 meet IEC 60730 safety requirements?
The R5F565N7FDFP#10 includes dedicated hardware features for IEC 60730 Class B compliance: oscillation-stoppage detection, CRC calculator (CRCA), independent watchdog timer (IWDTa) with window function, self-diagnostic A/D converter, register write protection, and memory protection unit (MPU). These features are documented in Renesas' functional safety manual for the RX65N Group and validated for use in certified industrial control applications.
What communication interfaces are integrated into the R5F565N7FDFP#10?
The R5F565N7FDFP#10 integrates Ethernet MAC (10/100 Mbps, RMII/MII), two CAN 2.0B channels (32 mailboxes each), SD host/slave/MMCIF, QSPI, three RSPI, three I²C (up to 1 Mbps), 13 SCI channels (including LIN-capable SCIh), USB 2.0 FS host/function/OTG, and parallel camera interface (PDC). All interfaces operate with independent clock domains (PCLKA/PCLKB) to avoid contention and ensure deterministic latency.
R5F565N7FDFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7FDFP#10 FAQ
1.How can I place an order for R5F565N7FDFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7FDFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7FDFP#10 reliable?
The price and inventory of R5F565N7FDFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7FDFP#10 is usually 5 days.
3.What payment methods are accepted for R5F565N7FDFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N7FDFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N7FDFP#10?
R5F565N7FDFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7FDFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7FDFP#10?
For technical support, including R5F565N7FDFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7FDFP#10 requirements.
6.How does Aetrix verify that R5F565N7FDFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N7FDFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7FDFP#10 meets industry standards.
7.What is the process for return or replacement of R5F565N7FDFP#10?
All R5F565N7FDFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7FDFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7FDFP#10 part is unused and in its original packaging.
Return procedure for R5F565N7FDFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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