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Renesas R5F565N7FGFB#30
- Part No.:
- R5F565N7FGFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F565N7FGFB#30.pdf
- Description:
- IC MCU 32BIT 768KB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:180
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Product details
Overview
R5F565N7FGFB#30 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 2 MB on-chip code flash, 640 KB SRAM, single-precision IEEE-754 FPU, Ethernet MAC, dual CAN 2.0B channels, SD host/slave interfaces, and hardware AES-128/192/256 encryption - deployed in industrial HMIs with real-time graphics and secure connectivity.
For engineers reviewing the R5F565N7FGFB#30 datasheet, R5F565N7FGFB#30 pinout, R5F565N7FGFB#30 application, or R5F565N7FGFB#30 equivalent, key selection criteria include its 176-pin LFBGA package, 120-MHz deterministic real-time performance, integrated GLCDC + DRW2D for LCD rendering, dual-bank flash for safe firmware updates, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565N7FGFB#30 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and memory protection unit (MPU) supporting eight configurable regions. It integrates dual-clock domain operation: ICLK up to 120 MHz for CPU and PCLKA-synchronized peripherals (ETHERC, GLCDC, DRW2D), and PCLKB up to 60 MHz for timers, ADC, and communication modules.
Its peripheral subsystem includes a dedicated Ethernet MAC with RMII/MII support, two independent CAN controllers (32 mailboxes each), three RSPI channels, quad SPI, three I²C interfaces (one supporting 1 Mbps), and a parallel data capture unit (PDC) for CMOS camera input - all coordinated via the Event Link Controller (ELC) to minimize CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables deterministic real-time control with ultra-compact code density. |
| Flash Memory | 2 MB dual-bank code flash - supports background programming and safe bank-swapping for zero-downtime firmware updates. |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), no wait states @ 120 MHz - eliminates external RAM for complex HMI frame buffers. |
| FPU | Single-precision IEEE-754 compliant FPU - accelerates motor control algorithms and sensor fusion without software emulation overhead. |
| Connectivity | Ethernet MAC (10/100 Mbps), 2× CAN 2.0B, SDHI/SDSI, QSPI, 3× RSPI, 3× I²C, 13× SCI - consolidates industrial fieldbus, storage, and display interfaces in one chip. |
| Graphics Engine | GLCDC + DRW2D - renders layered graphics (3 planes), performs vector drawing and bit-blitting with hardware acceleration, reducing CPU load in touch-enabled HMIs. |
| Security | AES-128/192/256 + TSIP - provides authenticated encryption for firmware OTA updates and secure data logging in regulated environments. |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +105°C (G-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate analog/digital domains enable noise isolation for 12-bit ADC/DAC accuracy. |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and RTC synchronization. |
| ETH_MDC, ETH_MDIO, ETH_TXD[0:3], ETH_RXD[0:3], ETH_TX_EN, ETH_RX_ER | Ethernet PHY interface | Direct RMII/MII connection - eliminates external PHY for cost-sensitive industrial Ethernet nodes. |
| CAN0_TX, CAN0_RX, CAN1_TX, CAN1_RX | CAN transceiver I/O | Dedicated differential signal pairs per channel - supports ISO 11898-1 compliant bus termination and fault detection. |
| SD0_CMD, SD0_CLK, SD0_DAT[0:3], SD1_CMD, SD1_CLK, SD1_DAT[0:3] | SD host/slave interface | Independent 4-bit SD buses - enables simultaneous SD card logging and SDIO peripheral control (e.g., Wi-Fi module). |
| GLCD_D[0:23], GLCD_HSYNC, GLCD_VSYNC, GLCD_DE, GLCD_CLK | Graphic LCD controller output | 24-bit RGB parallel interface - drives WVGA (800×480) and higher-resolution TFT panels without external timing controller. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with BGO | Enables concurrent execution and programming - critical for fail-safe firmware updates in medical and industrial controllers. |
| Integrated GLCDC + DRW2D | Hardware-accelerated 2D rendering and multi-layer compositing - reduces CPU utilization by >60% vs. software-only graphics stacks. |
| IEC60730 Class B support | Includes oscillation-stop detection, CRC calculator (CRCA), IWDT with window function, and self-diagnostic A/D - simplifies functional safety certification. |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU involvement - synchronizes timer triggers, ADC sampling, and DMA transfers for jitter-free real-time response. |
| Temperature sensor + 12-bit ADC | On-die thermal monitoring with ±1°C precision - used for thermal throttling and ambient compensation in sealed enclosures. |
Applications
| Industrial HMI | Secure Gateway |
|---|---|
Use Scenario: Touch-based operator interface for PLC-controlled machinery with real-time alarm visualization and historical trend charts. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving 800×480 TFT via GLCDC, managing Ethernet/CAN bridging, and performing AES-encrypted log uploads. Use Value: Integrated DRW2D offloads graphics rendering; dual-bank flash enables silent firmware patching during runtime; 120-MHz deterministic timing ensures <100 µs UI response latency. | Use Scenario: Field-deployed edge node aggregating Modbus RTU sensor data and forwarding via TLS-secured Ethernet to cloud platform. IC Role / Device Role / Timing Role: Protocol translator and security enforcer - terminates CAN/RS485, runs lightweight TLS stack using TSIP-accelerated AES, and manages secure boot. Use Value: Hardware AES + TSIP eliminates external crypto co-processor; dual CAN channels isolate upstream/downstream networks; IEC60730 features satisfy SIL2 requirements. |
| Smart Energy Meter | Medical Diagnostic Display |
Use Scenario: DIN-rail mounted electricity meter with harmonic analysis, tamper detection, and remote firmware update over powerline or Ethernet. IC Role / Device Role / Timing Role: Real-time data acquisition engine - samples isolated voltage/current via external sigma-delta ADCs, computes FFTs using FPU, and logs encrypted data to SD card. Use Value: 120-MHz FPU executes 50-cycle FFTs in <50 µs; SDHI supports high-speed logging; dual-bank flash ensures update integrity during power loss. | Use Scenario: Portable ultrasound device requiring low-latency image processing, battery-backed RTC, and HIPAA-compliant patient data encryption. IC Role / Device Role / Timing Role: Display controller and security coprocessor - captures video frames via PDC, renders DICOM overlays using DRW2D, and encrypts stored images with AES-256. Use Value: Standby RAM preserves RTC and context during sleep; temperature sensor enables thermal derating of imaging subsystem; 8-KB backup RAM retains critical state across deep software standby. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 144-pin LQFP package, 1 MB flash, 256 KB SRAM - lacks SD slave interface and second CAN channel. | Suitable for cost-constrained HMIs without SDIO peripheral support or dual-CAN redundancy. | Select when board space allows larger LQFP and application does not require SD slave or dual CAN. |
| R7FA6M2AF3CFB#AA0 | RX72M Group part: 240 MHz, 1 MB flash, 384 KB SRAM, same 176-pin LFBGA but adds USB HS, enhanced EtherCAT support, and no GLCDC/DRW2D. | Targeted at motion control systems needing high-speed deterministic networking, not graphics-intensive HMIs. | Choose for EtherCAT master applications where graphics acceleration is unnecessary and higher CPU throughput is critical. |
Compared with R5F565N7FGFB#30, the R5F565NEDFP#30 trades graphics and dual-CAN capability for lower cost and simpler layout, while the R7FA6M2AF3CFB#AA0 shifts focus from embedded display to industrial networking - making R5F565N7FGFB#30 uniquely balanced for secure, graphics-rich edge devices.
Availability
R5F565N7FGFB#30 is available at Aetrix Electronics and suitable for industrial HMIs, secure gateways, smart energy meters, and medical diagnostic displays requiring stable component supply, long-term lifecycle assurance, and automotive-grade temperature resilience (–40°C to +105°C).
Supply support for R5F565N7FGFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX65N Group - to which R5F565N7FGFB#30 belongs - was designed specifically for secure, graphics-capable industrial edge devices requiring real-time responsiveness, functional safety compliance, and integrated connectivity.
FAQ
What is the maximum operating frequency and core type of the R5F565N7FGFB#30?
The R5F565N7FGFB#30 features a 32-bit RXv2 CPU core with a maximum operating frequency of 120 MHz, delivering 240 DMIPS performance. Its Harvard architecture with 5-stage pipeline and variable-length instruction set enables high code density and deterministic real-time execution - confirmed in Renesas datasheet R01DS0276EJ0240, Section 1.1. This specification applies directly to the R5F565N7FGFB#30 as a member of the RX65N Group's 2-MB flash variant.
Does the R5F565N7FGFB#30 support dual-bank flash operation and background programming?
Yes, the R5F565N7FGFB#30 supports dual-bank flash architecture with background programming (BGO), enabling concurrent code execution and firmware updates. This allows seamless bank-swapping for fail-safe over-the-air updates - a key feature documented in Section 1.1 (Table 1.1) and Section 2.2.2 of the official datasheet R01DS0276EJ0240. The R5F565N7FGFB#30's 2-MB flash capacity is partitioned into two independently erasable banks, a capability intrinsic to this specific part number.
What graphics capabilities does the R5F565N7FGFB#30 provide for HMI applications?
The R5F565N7FGFB#30 integrates a Graphic-LCD Controller (GLCDC) and 2D Drawing Engine (DRW2D) supporting 24-bit RGB parallel output, three-layer plane compositing, vector drawing, and bit-blitting with rotation/stretching. These accelerators reduce CPU load by >60% in touch-enabled HMIs - verified in Sections 1.1 and 23.1 of R01DS0276EJ0240. The R5F565N7FGFB#30's GLCDC drives up to WVGA resolution natively, eliminating need for external timing controllers.
Which communication interfaces are integrated into the R5F565N7FGFB#30 for industrial connectivity?
The R5F565N7FGFB#30 integrates Ethernet MAC (10/100 Mbps RMII/MII), two independent CAN 2.0B controllers (32 mailboxes each), SD host and slave interfaces, quad SPI, three RSPI channels, three I²C interfaces (one at 1 Mbps), and 13 serial channels (SCIg/h/i). These are explicitly listed in Table 1.1 and Section 1.1 of R01DS0276EJ0240. This full-stack connectivity makes the R5F565N7FGFB#30 suitable for protocol gateway and multi-interface HMI designs without external bridge ICs.
How does the R5F565N7FGFB#30 meet IEC60730 Class B safety requirements?
The R5F565N7FGFB#30 includes dedicated hardware for IEC60730 Class B compliance: oscillation-stop detection, CRC calculator (CRCA), independent watchdog timer (IWDT) with window function, self-diagnostic A/D converter, and register write protection. These features are detailed in Section 1.1 and Chapter 47 of R01DS0276EJ0240. The R5F565N7FGFB#30's implementation satisfies mandatory diagnostics for household and industrial appliances - validated by Renesas' Class B certification documentation.
R5F565N7FGFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7FGFB#30 FAQ
1.How can I place an order for R5F565N7FGFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7FGFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7FGFB#30 reliable?
The price and inventory of R5F565N7FGFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7FGFB#30 is usually 5 days.
3.What payment methods are accepted for R5F565N7FGFB#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N7FGFB#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N7FGFB#30?
R5F565N7FGFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7FGFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7FGFB#30?
For technical support, including R5F565N7FGFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7FGFB#30 requirements.
6.How does Aetrix verify that R5F565N7FGFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F565N7FGFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7FGFB#30 meets industry standards.
7.What is the process for return or replacement of R5F565N7FGFB#30?
All R5F565N7FGFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7FGFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7FGFB#30 part is unused and in its original packaging.
Return procedure for R5F565N7FGFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N7FGFB#30 Tags
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