Renesas R5F565N7FGLK#20
- Part No.:
- R5F565N7FGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F565N7FGLK#20.pdf
- Description:
- IC MCU 32BIT 768KB FLSH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F565N7FGLK#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2-MB on-chip code flash (dual-bank), 640-KB SRAM, Ethernet MAC, CAN, SD host/slave, QSPI, and hardware AES/TSIP encryption - deployed in industrial HMI, networked gateways, and secure IoT edge controllers.
For engineers reviewing the R5F565N7FGLK#20 datasheet, R5F565N7FGLK#20 pinout, R5F565N7FGLK#20 application, or R5F565N7FGLK#20 equivalent, key selection criteria include its 176-pin LFBGA package, -40°C to +105°C operating range (G-version), dual-bank flash for safe firmware updates, 12-bit dual A/D converters (29 total channels), and integrated GLCDC + DRW2D for embedded graphics acceleration.
Technical Context
The R5F565N7FGLK#20 implements the RXv2 CPU core with IEEE-754 single-precision FPU, 5-stage CISC Harvard pipeline, and variable-length instructions enabling ultra-compact code. It supports memory protection (MPU), Trusted Memory (TM) for code confidentiality, and register write protection for IEC60730 compliance.
Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator. Peripheral clocks are independently configurable: ICLK up to 120 MHz, PCLKA up to 120 MHz (for ETHERC, AES, GLCDC), PCLKB up to 60 MHz (for TMR, CMT, S12AD unit 0), and PCLKD up to 60 MHz (for S12AD unit 1).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline and 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic execution in motor control and protocol stacks |
| Flash Memory | 2 Mbytes code flash with dual-bank structure - allows background programming and seamless bank switching during runtime |
| SRAM | 640 Kbytes total: 256 KB main RAM + 384 KB expansion RAM, all accessible at 120 MHz with zero wait states |
| A/D Converter | Dual 12-bit S12AD units: Unit 0 (8 channels), Unit 1 (21 channels); conversion time as low as 0.48 µs per channel |
| Package & Pins | LFBGA-176 (PLQP0176KB-A, 24 × 24 mm, 0.5-mm pitch); 136 general-purpose I/O pins with 5-V tolerance on 19 pins |
| Operating Temperature | G-version: –40°C to +105°C - qualified for under-hood automotive gateway and industrial PLC applications |
| Security Features | Hardware AES (128/192/256-bit keys) + Trusted Secure IP (TSIP) for key management and secure boot |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 × 24 mm, 0.5-mm ball pitch, RoHS-compliant, lead-free matte tin finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate analog/digital domains: AVCC0 powers ADC unit 0 and reference; AVCC1 powers ADC unit 1 and DAC; VCC powers digital logic |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise timing; required for Ethernet MAC and USB 2.0 FS operation |
| ETH_MDC, ETH_MDIO, ETH_TXD[0:3], ETH_RXD[0:3], ETH_TX_EN, ETH_RX_ER | Ethernet PHY interface | Direct MII interface - no external PHY needed; supports 10/100 Mbps full/half-duplex with IEEE 802.3x flow control |
| USB_VBUS, USB_DP, USB_DM, USB_ID | USB 2.0 Full-Speed transceiver | Integrated USB device/host/OTG controller with 2 KB on-chip buffer; supports bus-powered and self-powered modes |
| SD0_CLK, SD0_CMD, SD0_DAT[0:3], SD0_CD, SD0_WP | SD host interface signals | 1- or 4-bit SD bus supporting SD memory cards and SDIO peripherals up to 25 MB/s (high-speed mode) |
| QSPI_IO0–QSPI_IO3, QSPI_CLK, QSPI_SSL | Quad SPI interface | Direct connection to quad-output serial flash (e.g., Winbond W25Q series); supports single/dual/quad I/O modes |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Graphics Subsystem | GLCDC + DRW2D enables direct driving of TFT-LCD panels up to WXGA (1366×768) with hardware-accelerated 2D drawing (blitting, rotation, vector lines) |
| Dual-Bank Flash Architecture | Enables over-the-air (OTA) firmware updates without halting application execution - critical for unattended industrial gateways |
| Hardware Crypto Engine | AES-128/192/256 + TSIP provides certified cryptographic operations (encryption, decryption, key wrapping) without software overhead or side-channel exposure |
| Real-Time Communication Stack Support | On-chip Ethernet MAC, dual CAN 2.0B channels (32 mailboxes each), and multiple SCI/RSPI/QSPI interfaces simplify implementation of PROFINET, CANopen, and Modbus TCP |
| IEC60730 Class B Compliance Ready | Built-in oscillation-stop detection, CRC calculator (CRCA), IWDT with window function, A/D self-diagnostic, and register write protection meet functional safety requirements |
| Low-Power Operation | 0.19 mA/MHz typical active current; four low-power modes including deep software standby with 8 KB battery-backed RAM retention |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Standalone touch-based operator interface for factory-floor machinery with local data logging and alarm visualization. IC Role / Device Role / Timing Role: Main application processor running RTOS, driving 7-inch TFT-LCD via GLCDC, capturing touch input via SCI/ADC, and storing logs in data flash. Use Value: Integrated DRW2D accelerates UI rendering; dual-bank flash enables silent firmware upgrades; 12-bit A/D monitors analog sensor inputs directly. |
Use Scenario: Protocol-translation gateway connecting legacy CAN field devices to cloud via Ethernet/Wi-Fi (external PHY) and TLS-secured MQTT. IC Role / Device Role / Timing Role: Central controller executing CANopen stack, Ethernet TCP/IP stack, and TLS handshake using hardware AES/TSIP. Use Value: On-chip Ethernet MAC eliminates external PHY cost; hardware crypto offloads TLS processing; RTC + battery backup maintains time across power cycles. |
| Automotive Diagnostic Tool | Smart Energy Meter Interface |
Use Scenario: Handheld OBD-II scanner with USB-C connectivity, CAN bus analysis, and firmware update capability via SD card. IC Role / Device Role / Timing Role: USB host/device controller interfacing with PC or smartphone; dual CAN modules monitoring J1939 and ISO 15765 traffic. Use Value: Integrated USB 2.0 FS eliminates external transceiver; 21-channel A/D unit monitors internal voltage/current sensors; SDHI reads calibration files from removable card. |
Use Scenario: DIN-rail mounted meter concentrator aggregating data from RS485-connected smart meters and transmitting via Ethernet to utility backend. IC Role / Device Role / Timing Role: Multi-protocol bridge handling Modbus RTU (SCI), DLMS/COSEM (Ethernet), and secure firmware delivery (AES-encrypted OTA). Use Value: Dual CAN and 11-channel SCI support concurrent fieldbus polling; TSIP secures firmware images; 8 KB standby RAM preserves metering counters during brownouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFLK#20 | Same RX65N Group, identical 176-pin LFBGA package, but with 1-MB flash and 256-KB SRAM (not 2-MB/640-KB) | Suitable for cost-sensitive designs where full 2-MB flash and graphics acceleration are not required | Select when firmware size < 1 MB and GLCDC/DRW2D usage is minimal or absent |
| R5F566TEBGLK#20 | RX66T Group part; same pinout (176-LFBGA), 160-MHz CPU, enhanced MTU3 timers optimized for motor control, no GLCDC/DRW2D | Targeted at servo drives and inverters requiring high-resolution PWM and encoder interfaces, not display subsystems | Choose for real-time motor control with >120-MHz timing precision; avoid if LCD or SDIO functionality is essential |
Compared with R5F565N7FGLK#20, R5F565NEDFLK#20 reduces memory capacity while retaining identical peripheral set and package, whereas R5F566TEBGLK#20 trades graphics and storage interfaces for higher-performance timer subsystems - making each alternative optimal only within distinct application boundaries.
Availability
R5F565N7FGLK#20 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and automotive diagnostic tools requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for R5F565N7FGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX65N Group - including R5F565N7FGLK#20 - was designed specifically for secure, graphics-enabled industrial edge applications requiring real-time Ethernet, CAN, and cryptographic capabilities in extended temperature environments.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565N7FGLK#20?
The R5F565N7FGLK#20 features a 32-bit RXv2 CPU core with a maximum operating frequency of 120 MHz, delivering 240 DMIPS performance. Its CISC Harvard architecture includes a 5-stage pipeline, variable-length instructions, and IEEE-754 single-precision floating-point unit - enabling deterministic real-time execution for industrial control and protocol stacks.
Does the R5F565N7FGLK#20 support dual-bank flash for safe firmware updates?
Yes, the R5F565N7FGLK#20 includes 2 Mbytes of on-chip code flash organized in a dual-bank structure. This allows background programming of one bank while executing code from the other, enabling seamless over-the-air (OTA) firmware updates without application interruption - a critical capability for remote industrial gateways and unattended systems.
What graphics capabilities does the R5F565N7FGLK#20 provide?
The R5F565N7FGLK#20 integrates both a Graphic-LCD Controller (GLCDC) and a 2D Drawing Engine (DRW2D). The GLCDC supports TFT-LCD panels up to WXGA resolution (1366×768) with three overlay planes; the DRW2D accelerates bit blitting, rotation, scaling, and vector drawing - eliminating the need for external GPU in embedded HMI designs.
Which communication interfaces are integrated into the R5F565N7FGLK#20?
The R5F565N7FGLK#20 integrates Ethernet MAC (MII interface), dual CAN 2.0B channels (32 mailboxes each), USB 2.0 Full-Speed host/function/OTG, SD host/slave, MMCIF, QSPI, RSPI, multiple SCI channels (including LIN-capable SCIh), I2C, and parallel camera interface (PDC) - providing comprehensive connectivity for industrial networking and multi-protocol edge devices.
Is the R5F565N7FGLK#20 qualified for extended temperature operation?
Yes, the R5F565N7FGLK#20 is the G-version part, rated for operation from –40°C to +105°C. This qualification meets automotive under-hood and industrial control cabinet requirements, and is validated across the full specification - including Ethernet MAC timing, flash programming, and analog peripheral accuracy - within this extended range.
R5F565N7FGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 768KB (768K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N7FGLK#20 FAQ
1.How can I place an order for R5F565N7FGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N7FGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N7FGLK#20 reliable?
The price and inventory of R5F565N7FGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N7FGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F565N7FGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N7FGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N7FGLK#20?
R5F565N7FGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N7FGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N7FGLK#20?
For technical support, including R5F565N7FGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N7FGLK#20 requirements.
6.How does Aetrix verify that R5F565N7FGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F565N7FGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N7FGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F565N7FGLK#20?
All R5F565N7FGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N7FGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N7FGLK#20 part is unused and in its original packaging.
Return procedure for R5F565N7FGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N7FGLK#20 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

