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Renesas R5F565N9AGFB#30
- Part No.:
- R5F565N9AGFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F565N9AGFB#30.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:180
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Product details
Overview
R5F565N9AGFB#30 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 2 MB on-chip code flash, 640 KB SRAM, single-precision IEEE-754 FPU, Ethernet MAC, dual CAN channels, SD host/slave interfaces, and hardware AES/TSIP encryption. It targets industrial HMI, networked gateway, and secure IoT edge node applications requiring real-time control, connectivity, and cryptographic integrity.
For engineers reviewing the R5F565N9AGFB#30 datasheet, R5F565N9AGFB#30 pinout, R5F565N9AGFB#30 application, or R5F565N9AGFB#30 equivalent, key selection criteria include its 176-pin LFBGA package, 120-MHz deterministic timing, dual-bank flash for safe firmware updates, integrated GLCDC+DRW2D for embedded graphics, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565N9AGFB#30 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a dedicated 120-kHz IWDT clock source, MPU with eight configurable protection areas, and Trusted Memory (TM) for secure code execution from protected flash regions.
Its peripheral subsystem includes an Ethernet MAC with RMII/MII support, two CAN 2.0B controllers (32 mailboxes each), and three independent serial interfaces (SCIg/h/i) supporting asynchronous, SPI-like, and I²C-like modes - all coordinated via the Event Link Controller (ELC) to minimize CPU intervention in time-critical signal chains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe bank switching during runtime |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| FPU | Single-precision IEEE-754 compliant floating-point unit supporting 32-bit operations |
| Connectivity | Ethernet MAC (10/100 Mbps), 2× CAN 2.0B, 3× RSPI, 1× QSPI, 3× I²C (up to 1 Mbps), SDHI/SDSI/MMCIF |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), 2× 12-bit D/A converters, on-die temperature sensor (±1°C) |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), CRC calculator (8-/32-bit), register write protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) rails enable noise isolation for ADC/DAC operation |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and RTC reference |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC interface for PHY configuration and status monitoring |
| CAN0_TX / CAN0_RX | Channel 0 CAN differential pair | Direct connection to external CAN transceiver; supports ISO 11898-1 standard frame and extended frame |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); compatible with SD memory and SDIO cards per Physical Layer Spec v3.01 |
| GLCD_D0–23 / GLCD_HSYNC / VSYNC | Graphic LCD controller outputs | 24-bit parallel RGB interface with programmable timing for direct drive of TFT panels up to VGA resolution |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates without halting real-time operation; one bank executes while the other is reprogrammed |
| Integrated GLCDC + DRW2D | Hardware-accelerated 2D graphics rendering and multi-layer LCD composition eliminate CPU overhead for UI rendering |
| IEC60730 safety support | Includes oscillation-stop detection, CRC calculation, IWDT windowing, self-diagnostic A/D, and register write protection for Class B compliance |
| Event Link Controller (ELC) | 83 internal event sources can trigger peripheral actions (e.g., timer-triggered ADC conversion) without CPU involvement |
| Trusted Secure IP (TSIP) | Hardware-accelerated cryptographic engine supporting AES, SHA, RSA, and key management with tamper-resistant key storage |
Applications
| Industrial HMI Panel | Secure Gateway Device |
|---|---|
Use Scenario: Embedded touchscreen panel in factory automation with local logic, data logging, and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Primary application processor managing GUI rendering via GLCDC/DRW2D, executing control algorithms on RXv2 core, and handling EtherCAT or Modbus TCP via Ethernet MAC. Use Value: 640 KB SRAM enables full-featured UI framework; dual-bank flash allows field-upgradable firmware without downtime; TSIP secures OTA update integrity. | Use Scenario: Edge gateway aggregating data from CAN-based sensors and legacy fieldbus devices, then forwarding to cloud via TLS-secured Ethernet. IC Role / Device Role / Timing Role: Central protocol translator and security enforcer - bridging CAN 2.0B networks to encrypted Ethernet using hardware AES and dual CAN controllers. Use Value: Two independent CAN channels (32 mailboxes each) support concurrent multi-network monitoring; hardware TSIP accelerates TLS handshake and payload encryption. |
| Medical Data Logger | Smart Energy Meter |
Use Scenario: Battery-backed portable device capturing physiological signals (ECG, SpO₂) and storing encrypted logs to SD card. IC Role / Device Role / Timing Role: Real-time acquisition controller interfacing analog front-end via 12-bit S12AD, managing SDHI/SDSI for local storage, and maintaining accurate time via RTC with battery backup. Use Value: On-die temperature sensor calibrates ADC drift; standby RAM preserves context during low-power sleep; IEC60730 features satisfy medical device functional safety requirements. | Use Scenario: Revenue-grade meter with pulse input counting, tamper detection, and secure firmware updates over powerline or cellular backhaul. IC Role / Device Role / Timing Role: Metrology co-processor synchronizing pulse capture (via TPU/MTU3), performing energy calculations, and enforcing secure boot and update validation via TSIP and MPU. Use Value: Hardware CRC and register write protection prevent unauthorized configuration changes; dual-bank flash ensures fail-safe firmware rollback after update failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, but 144-pin LFQFP package, 1 MB flash, 256 KB SRAM, no Ethernet MAC or GLCDC | Suitable for cost-sensitive, space-constrained control-only applications without display or Ethernet | Select when Ethernet, graphics, or >1 MB flash are unnecessary and LFBGA assembly is not available. |
| R5F566TEADFP#30 | RX66T Group part: higher 160-MHz CPU, enhanced MTU3 for motor control, no TSIP or GLCDC, different pinout | Optimized for real-time motor drive with PWM precision; lacks security and display peripherals | Choose for servo/inverter control where deterministic PWM timing outweighs crypto/display needs. |
Compared with R5F565N9AGFB#30, R5F565NEDFP#30 reduces footprint and cost by removing Ethernet, graphics, and half the memory - ideal for compact control nodes. R5F566TEADFP#30 trades security and UI capability for superior motor-control timing and higher CPU throughput, making it unsuitable for secure gateway or HMI roles despite shared ecosystem tooling.
Availability
R5F565N9AGFB#30 is available at Aetrix Electronics and suitable for industrial HMI, secure gateway, medical data logging, and smart energy metering applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F565N9AGFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group, including R5F565N9AGFB#30, was designed for secure, connected industrial edge devices requiring real-time performance, rich connectivity (Ethernet/CAN/SD), and hardware-enforced safety and security.
FAQ
What is the maximum operating frequency and core type of the R5F565N9AGFB#30?
The R5F565N9AGFB#30 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a 5-stage pipeline, Harvard architecture, and support for IEEE-754 single-precision floating-point arithmetic. Its instruction set enables ultra-compact code density, reducing flash usage and improving cache efficiency in the R5F565N9AGFB#30.
Does the R5F565N9AGFB#30 support secure firmware updates and cryptographic acceleration?
Yes, the R5F565N9AGFB#30 integrates Trusted Secure IP (TSIP) for hardware-accelerated AES-128/192/256 encryption and key management, plus a CRC calculator supporting 8- and 32-bit polynomials. Its dual-bank flash architecture allows background programming of one bank while executing from the other - enabling atomic, fail-safe firmware updates. These features are essential for secure OTA deployment in the R5F565N9AGFB#30.
What display and graphics capabilities does the R5F565N9AGFB#30 provide?
The R5F565N9AGFB#30 includes a Graphic-LCD Controller (GLCDC) supporting 24-bit RGB parallel output and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing, bit blitting, rotation, and layer composition. It manages up to three display planes (background, graphic 1, graphic 2) and supports CLUT-based and true-color pixel formats. These peripherals offload UI rendering from the RXv2 core in the R5F565N9AGFB#30, enabling responsive touch-enabled HMIs.
How many CAN channels and Ethernet interfaces does the R5F565N9AGFB#30 integrate?
The R5F565N9AGFB#30 integrates two independent CAN 2.0B controllers (CAN0 and CAN1), each supporting 32 mailboxes and full ISO 11898-1 compliance. It also includes a full-featured Ethernet MAC supporting 10/100 Mbps in both full- and half-duplex modes, with MII/RMII physical layer interface support and integrated EDMAC for descriptor-based DMA transfers - all implemented directly on-die in the R5F565N9AGFB#30.
What is the package type and pin count of the R5F565N9AGFB#30?
The R5F565N9AGFB#30 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 × 24 mm with 0.5-mm ball pitch. This LFBGA package supports high I/O density (136 general-purpose pins, 19 5-V-tolerant) and thermal performance required for industrial applications. The exact mechanical and soldering specifications for the R5F565N9AGFB#30 are defined in Renesas document MS0011-A.
R5F565N9AGFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N9AGFB#30 FAQ
1.How can I place an order for R5F565N9AGFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N9AGFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N9AGFB#30 reliable?
The price and inventory of R5F565N9AGFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N9AGFB#30 is usually 5 days.
3.What payment methods are accepted for R5F565N9AGFB#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N9AGFB#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N9AGFB#30?
R5F565N9AGFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N9AGFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N9AGFB#30?
For technical support, including R5F565N9AGFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N9AGFB#30 requirements.
6.How does Aetrix verify that R5F565N9AGFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F565N9AGFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N9AGFB#30 meets industry standards.
7.What is the process for return or replacement of R5F565N9AGFB#30?
All R5F565N9AGFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N9AGFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N9AGFB#30 part is unused and in its original packaging.
Return procedure for R5F565N9AGFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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