Renesas R5F565N9BGFB#30

Overview

R5F565N9BGFB#30 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, and Ethernet MAC + PHY. It integrates CAN 2.0B (2 channels), SD host/slave, QSPI, GLCDC, DRW2D, and hardware AES-128/192/256 for industrial HMI and networked edge controllers.

For engineers reviewing the R5F565N9BGFB#30 datasheet, R5F565N9BGFB#30 pinout, R5F565N9BGFB#30 application, or R5F565N9BGFB#30 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C operating range (G-version), 12-bit dual A/D converters (29 total channels), 2-channel 12-bit D/A, and IEC60730 safety features including CRCA, IWDTa, and register write protection.

Technical Context

The R5F565N9BGFB#30 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling ultra-compact code and 240 DMIPS at 120 MHz. It includes single-precision IEEE-754 FPU, two MAC units, and 32-bit multiplier with one-cycle execution.

Its clock system supports external crystal (8–24 MHz) or internal PLL, with independent domain clocks: ICLK up to 120 MHz (CPU), PCLKA up to 120 MHz (ETHERC, GLCDC, DRW2D), PCLKB up to 60 MHz (most peripherals), and dedicated ADCLKs for S12AD units. The device uses a memory protection unit (MPU) with eight configurable regions and Trusted Memory (TM) for secure code execution.

Key Specifications

Pinout & Package

Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, lead-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit industrial MCU applications.

Compared with R5F565N9BGFB#30, the R5F565NEBDFP#30 trades PHY integration and memory size for smaller footprint and lower cost, while the R5F566TEBDFP#30 shifts focus entirely to motor control timing precision at the expense of connectivity and graphics capability.

Availability

R5F565N9BGFB#30 is available at Aetrix Electronics and suitable for industrial HMI, smart gateways, medical data loggers, and building automation nodes requiring stable component supply, long lifecycle assurance, and automotive-grade temperature resilience.

Supply support for R5F565N9BGFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader delivering trusted microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.

The RX65N Group-including R5F565N9BGFB#30-is designed for high-integration industrial edge devices requiring real-time connectivity, functional safety, graphics, and secure firmware update capabilities.

FAQ

What is the maximum operating frequency and CPU performance of the R5F565N9BGFB#30?

The R5F565N9BGFB#30 operates at a maximum system clock frequency of 120 MHz using the RXv2 CPU core. It delivers 240 DMIPS of processing performance and includes a single-precision IEEE-754 floating-point unit, two multiply-and-accumulate units, and a 32-bit multiplier with one-cycle instruction execution. This enables deterministic real-time control and efficient signal processing in demanding industrial applications.

Does the R5F565N9BGFB#30 include an integrated Ethernet PHY?

Yes, the R5F565N9BGFB#30 integrates both an Ethernet MAC and a full IEEE 802.3-compliant PHY supporting 10/100 Mbps in full- and half-duplex modes. It supports MII and RMII interfaces and includes wake-on-LAN (WoL) and flow control per IEEE 802.3x. No external PHY IC is required, reducing BOM cost and board space for networked edge devices.

What safety and security features does the R5F565N9BGFB#30 provide for IEC60730 compliance?

The R5F565N9BGFB#30 includes multiple IEC60730-certifiable features: oscillation-stoppage detection, hardware CRC calculator (CRCA) for 8-/32-bit data, independent watchdog timer (IWDTa) with configurable window function, self-diagnostic A/D converter, register write protection, and Trusted Secure IP (TSIP) for AES encryption. These features collectively support Class B compliance in safety-critical embedded systems.

How much SRAM and flash memory does the R5F565N9BGFB#30 have, and what are their access characteristics?

The R5F565N9BGFB#30 includes 640 KB of on-chip SRAM with zero wait states at 120 MHz, and 2 MB of dual-bank code flash memory. Flash access is zero-wait up to 50 MHz (or on cache hit at 120 MHz), one-wait up to 100 MHz, and two-wait above 100 MHz. The dual-bank structure allows background programming and safe bank-swapping for robust firmware updates.

What graphics and display capabilities does the R5F565N9BGFB#30 support?

The R5F565N9BGFB#30 integrates a Graphic-LCD Controller (GLCDC) supporting up to three overlay planes (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) for vector drawing, bit blitting, rotation, and stretching. It supports 32-/16-/8-bit pixel formats and CLUT-based color conversion-enabling rich, responsive HMIs without external GPU or frame buffer RAM.