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Renesas R5F565N9BGLK#20
- Part No.:
- R5F565N9BGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F565N9BGLK#20.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F565N9BGLK#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2-Mbyte dual-bank code flash, 640-Kbyte SRAM, Ethernet MAC, CAN 2.0B (2 channels), SD host/slave interfaces, and hardware AES-128/192/256 encryption - deployed in industrial HMI, networked gateway, and secure IoT edge node applications.
For engineers reviewing the R5F565N9BGLK#20 datasheet, R5F565N9BGLK#20 pinout, R5F565N9BGLK#20 application, or R5F565N9BGLK#20 equivalent, key selection criteria include Ethernet + CAN coexistence, 136-pin LFBGA package compatibility, 120-MHz real-time deterministic execution, dual-bank flash for safe firmware updates, and TSIP-based secure boot support.
Technical Context
The R5F565N9BGLK#20 implements the RXv2 CPU core with IEEE-754 single-precision FPU, 240 DMIPS at 120 MHz, and CISC Harvard architecture with 5-stage pipeline. It integrates a memory protection unit (MPU), Trusted Secure IP (TSIP), and register write protection to meet IEC 60730 Class B requirements.
Its clock system supports external crystal (8–24 MHz) or internal PLL, with independent PCLKA (up to 120 MHz) for Ethernet, DRW2D, and GLCDC, and PCLKB (up to 60 MHz) for ADC, timers, and serial peripherals. The device uses a 176-pin LFBGA (PLQP0176KB-A, 24 × 24 mm, 0.5-mm pitch) package with 136 general-purpose I/O pins, 19 of which are 5-V tolerant.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 Mbytes code flash with dual-bank structure enabling background programming and safe firmware swap |
| SRAM | 640 Kbytes on-chip SRAM (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| Peripherals | Ethernet MAC (10/100 Mbps), CAN 2.0B (2 channels, 32 mailboxes each), SDHI/SDSI/MMCIF, QSPI, 3× RSPI, 13× SCI, 3× RIIC, GLCDC, DRW2D, PDC |
| Analog | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A converters, on-chip temperature sensor (±1°C) |
| Security | AES-128/192/256 engine + TSIP module supporting secure boot, key wrapping, and cryptographic acceleration |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, 136 GPIOs (19 × 5-V tolerant) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5-mm ball pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core (2.7–3.6 V), analog unit 0, and analog unit 1 supplies - independently decoupled for noise isolation |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/clock retention without system reset |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise timing; required for Ethernet MAC clock stability |
| ETH_MDC / ETH_MDIO | IEEE 802.3 management interface | Enables PHY configuration and status polling via SMI; essential for auto-negotiation and link monitoring |
| CAN0_TX / CAN0_RX | Channel 0 CAN differential pair | Direct connection to ISO 11898-1 compliant transceiver; supports bit rates up to 1 Mbps |
| SD0_CLK / SD0_CMD / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); enables local storage and firmware update via SD card |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates with zero downtime: one bank executes while the other is reprogrammed |
| Trusted Secure IP (TSIP) | Hardware-accelerated AES and secure key storage prevent firmware extraction and enable authenticated boot |
| Ethernet + CAN co-integration | Simultaneous real-time protocol handling: CAN for fieldbus control, Ethernet for cloud connectivity and OTA updates |
| GLCDC + DRW2D graphics subsystem | Offloads GUI rendering from CPU: supports 3-layer overlay, 32-bit color depth, and vector/bit-blit operations |
| IEC 60730 safety features | Includes oscillation-stop detection, CRC calculator (CRCA), IWDT windowing, and self-diagnostic A/D test modes |
| Event Link Controller (ELC) | Hardware-triggered peripheral chaining (e.g., TPU → A/D start → DMA transfer) eliminates CPU intervention latency |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor managing GLCDC-driven TFT display, touch controller SPI, SDHI for log storage, and Ethernet for Modbus TCP/IP communication. Use Value: 640-KB SRAM buffers full GUI assets; dual-bank flash allows field-upgradable UI firmware without halting machine operation. |
Use Scenario: Protocol translator bridging CAN-based sensors and Ethernet/WiFi-connected SCADA systems in building automation. IC Role / Device Role / Timing Role: Real-time protocol gateway executing CAN message parsing, data aggregation, and Ethernet frame encapsulation with deterministic latency. Use Value: Integrated CAN 2.0B (2 channels) and Ethernet MAC eliminate external bridge ICs; TSIP secures firmware updates over untrusted networks. |
| Secure IoT Edge Node | Medical Data Logger |
Use Scenario: Battery-powered wearable or portable diagnostic device requiring encrypted sensor data transmission and tamper-resistant firmware. IC Role / Device Role / Timing Role: Secure host MCU performing AES-encrypted BLE/Ethernet upload, A/D acquisition from biopotential sensors, and RTC-timestamped event logging. Use Value: TSIP + AES engine enables end-to-end data confidentiality; 8-KB standby RAM preserves session state during deep sleep between measurements. |
Use Scenario: Portable ECG or vital sign monitor capturing analog biosignals, applying digital filtering, and storing annotated waveforms to SD card. IC Role / Device Role / Timing Role: High-precision signal acquisition controller using dual 12-bit A/D units (21-channel unit 1 for multi-lead ECG), DRW2D for waveform rendering, and SDHI for DICOM-compliant storage. Use Value: 0.48 µs per-channel A/D conversion time ensures >2 MSPS aggregate sampling; self-diagnostic A/D mode validates analog path integrity pre-measurement. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEBGLK#20 | Same RX65N family, identical 176-pin LFBGA package, but with 1.5-Mbyte flash and 256-KB SRAM (not 640 KB) | Suitable where firmware size < 1.5 MB and GUI complexity is reduced; lacks expansion RAM for large framebuffer allocation | Select when cost optimization is prioritized and full 640-KB SRAM is unnecessary for target HMI resolution and animation depth |
| R5F566NHBGLK#20 | RX66N family successor: 160-MHz RXv3 core, 2-MB flash, 1-MB SRAM, enhanced TSIP-Lite, no GLCDC/DRW2D | Higher compute throughput and security, but removes integrated graphics - requires external GPU or simplified UI | Choose for next-gen gateways needing faster crypto or AI inference, accepting external display driver for higher-resolution panels |
Compared with R5F565N9BGLK#20, the R5F565NEBGLK#20 reduces memory capacity for cost-sensitive deployments, while the R5F566NHBGLK#20 trades integrated graphics for higher CPU performance and advanced security - both require PCB layout verification due to non-pin-compatible ball maps despite shared footprint family.
Availability
R5F565N9BGLK#20 is available at Aetrix Electronics and suitable for industrial HMI, smart gateway, and secure IoT edge node applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F565N9BGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The RX65N Group - including R5F565N9BGLK#20 - was designed for secure, connected industrial devices requiring real-time Ethernet/CAN convergence, rich human-machine interaction, and functional safety compliance.
FAQ
What is the maximum operating frequency and core type of the R5F565N9BGLK#20?
The R5F565N9BGLK#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. It delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit. This core enables deterministic real-time execution for industrial control and protocol stack processing within the R5F565N9BGLK#20.
Does the R5F565N9BGLK#20 support dual-bank flash for firmware updates?
Yes, the R5F565N9BGLK#20 includes 2 Mbytes of on-chip code flash memory with a dual-bank structure. This allows background programming of one bank while executing from the other, enabling safe over-the-air or local firmware updates without system interruption - a critical capability implemented directly in the R5F565N9BGLK#20 silicon.
Which communication interfaces are integrated into the R5F565N9BGLK#20?
The R5F565N9BGLK#20 integrates Ethernet MAC (10/100 Mbps), two CAN 2.0B channels (32 mailboxes each), SD host/slave interfaces, quad SPI, three RSPI, 13 SCI channels, three I²C interfaces, USB 2.0 FS host/function, and MMCIF. These interfaces are natively supported in hardware without external glue logic in the R5F565N9BGLK#20.
What security features does the R5F565N9BGLK#20 provide for embedded applications?
The R5F565N9BGLK#20 includes AES-128/192/256 encryption, Trusted Secure IP (TSIP) for key management and secure boot, memory protection unit (MPU), register write protection, CRC calculator (CRCA), and independent watchdog timer (IWDT) with windowing. These features are silicon-hardened and documented for IEC 60730 compliance in the R5F565N9BGLK#20 datasheet.
What is the package type and pin count of the R5F565N9BGLK#20?
The R5F565N9BGLK#20 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 mm × 24 mm with 0.5-mm ball pitch. It provides 136 general-purpose I/O pins, 19 of which are 5-V tolerant - all confirmed in the official Renesas R01DS0276EJ0240 datasheet for the R5F565N9BGLK#20.
R5F565N9BGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N9BGLK#20 FAQ
1.How can I place an order for R5F565N9BGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N9BGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N9BGLK#20 reliable?
The price and inventory of R5F565N9BGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N9BGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F565N9BGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N9BGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N9BGLK#20?
R5F565N9BGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N9BGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N9BGLK#20?
For technical support, including R5F565N9BGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N9BGLK#20 requirements.
6.How does Aetrix verify that R5F565N9BGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F565N9BGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N9BGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F565N9BGLK#20?
All R5F565N9BGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N9BGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N9BGLK#20 part is unused and in its original packaging.
Return procedure for R5F565N9BGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N9BGLK#20 Tags
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