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Renesas R5F565N9EGFP#30
- Part No.:
- R5F565N9EGFP#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N9EGFP#30.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:270
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Product details
Overview
R5F565N9EGFP#30 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash, 640 KB SRAM, Ethernet MAC, dual CAN channels, SD host/slave interfaces, and hardware AES-128/192/256 encryption - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F565N9EGFP#30 datasheet, R5F565N9EGFP#30 pinout, R5F565N9EGFP#30 application, or R5F565N9EGFP#30 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), 120 MHz real-time deterministic execution, dual-bank flash for safe firmware updates, 12-bit dual A/D converters (29 total channels), and integrated GLCDC + DRW2D for embedded graphics acceleration.
Technical Context
The R5F565N9EGFP#30 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a single-precision IEEE-754 FPU, two MAC units, and a 32-bit multiplier executing in one cycle - supporting real-time control algorithms requiring floating-point math and fast signal processing.
Its clock system combines external crystal (8–24 MHz) with internal PLL, HOCO (16/18/20 MHz), and LOCO (240 kHz), feeding independent domain clocks: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for Ethernet/USB/GLCDC, and PCLKB up to 60 MHz for timers/A/D. The MPU enforces memory protection across eight configurable regions, while Trusted Secure IP (TSIP) provides hardware-accelerated cryptographic operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS - enables deterministic real-time control with low-latency interrupt response. |
| Memory | 2 MB code flash (dual-bank), 640 KB SRAM, 32 KB data flash - supports background programming and firmware swap without halting execution. |
| FPU & DSP | IEEE-754 single-precision FPU + two MAC units - accelerates motor control, sensor fusion, and digital filtering tasks. |
| Connectivity | Ethernet MAC (10/100 Mbps), 2× CAN (ISO 11898-1), 3× RSPI, 3× I²C, 13× SCI, QSPI, SDHI/SDSI, USB 2.0 FS - enables multi-protocol industrial networking. |
| Analog | Dual 12-bit S12AD (8 + 21 channels), 2× R12DA, on-die temperature sensor (±1°C) - supports high-resolution sensor acquisition and closed-loop analog output. |
| Security | AES-128/192/256 + TSIP + MPU + register write protection - meets IEC 60730 Class B requirements for functional safety. |
| Package | PLQP0176KB-A, 176-pin LFBGA, 24 × 24 mm, 0.5 mm pitch - provides 136 general-purpose I/O pins with 5-V tolerance and configurable drive strength. |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm ball pitch, 136 general-purpose I/O pins, 19 of which are 5-V tolerant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC) and analog (AVCC0/AVCC1) supplies ensure noise isolation for ADC/DAC operation. |
| XTAL / EXTAL | Main clock oscillator interface | Supports 8–24 MHz crystal for precise timing; optional external clock input. |
| RES# | Active-low reset input | Hardware reset assertion; synchronous release ensures reliable initialization sequence. |
| MD0 / MD1 | Mode setting pins | Select boot mode (SCI/USB/FINE) or single-chip operation at power-on reset. |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MII/RMII management bus for Ethernet PHY configuration. |
| TXD0 / RXD0 | SCI0 asynchronous serial I/O | Full-duplex UART interface for debug console or peripheral communication. |
| CRX0 / CTX0 | CAN0 differential transceiver I/O | Direct connection to ISO 11898-1 compliant CAN physical layer. |
| SD0_CLK / SD0_CMD / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s) for local storage or firmware update. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating system downtime. |
| Integrated GLCDC + DRW2D | Hardware-accelerated graphics rendering supports 3-plane overlay, 32-bit pixel formats, and vector/bit-blit operations - reduces CPU load in HMI applications. |
| Event Link Controller (ELC) | 83 internal event sources can trigger peripheral actions (e.g., timer-triggered ADC conversion) without CPU intervention - improves real-time determinism. |
| Trusted Secure IP (TSIP) | Hardware AES engine with key wrapping, RNG, and secure boot support - accelerates TLS handshake and firmware signature verification. |
| IEC 60730 safety functions | Oscillation-stop detection, CRC calculator (CRCA), IWDT windowing, and A/D self-diagnostic - simplifies Class B certification for industrial control. |
Applications
| Industrial HMI Controller | Secure Gateway Node |
|---|---|
Use Scenario: Embedded display controller for factory-floor HMIs with touch interface, real-time status visualization, and local alarm logging. IC Role / Device Role / Timing Role: Main application processor managing GLCDC, DRW2D, touchscreen SPI/I²C, and Ethernet backhaul - executes UI logic at 120 MHz with deterministic latency. Use Value: Integrated graphics engine eliminates external GPU, reducing BOM cost and PCB area; dual-bank flash enables over-the-air firmware updates without service interruption. | Use Scenario: Protocol translation gateway connecting Modbus RTU field devices to cloud via Ethernet/Wi-Fi (via external PHY). IC Role / Device Role / Timing Role: Central protocol stack processor handling CAN/Modbus parsing, TLS-secured MQTT transmission, and real-time scheduling via ELC-linked timers. Use Value: Hardware AES and TSIP accelerate TLS 1.2 handshake; dual CAN channels allow simultaneous connection to two PLC networks. |
| Networked Energy Meter | Smart Building Controller |
Use Scenario: DIN-rail mounted electricity meter with harmonic analysis, tamper detection, and remote firmware update capability. IC Role / Device Role / Timing Role: High-precision measurement unit using dual 12-bit ADCs (29-channel scan), temperature-compensated RTC, and SDHI for local data logging. Use Value: On-die temperature sensor enables automatic ADC offset calibration; 640 KB SRAM buffers 15-minute waveform capture at 16 kHz sampling. | Use Scenario: HVAC/BMS controller managing zone sensors, actuator PWM outputs, and building-wide BACnet/IP communication. IC Role / Device Role / Timing Role: Real-time scheduler coordinating MTU3 PWM outputs (fan speed, valve position), 12-bit DACs (analog setpoints), and Ethernet-based BACnet stack. Use Value: Complementary PWM mode with dead-time insertion ensures safe 3-phase inverter control; PCLKA-synchronized peripherals guarantee jitter-free timing for HVAC loop closure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEGFP#30 | Same RX65N Group, identical 176-pin LFBGA package, but with 1 MB code flash and 256 KB SRAM instead of 2 MB/640 KB. | Suitable for cost-sensitive designs where full memory capacity is not required; lacks dual-bank flash for live firmware updates. | Select when application firmware size remains under 1 MB and background programming is not mandatory. |
| R5F566TEGFP#30 | RX66T Group part in same 176-pin LFBGA; higher 160 MHz CPU, enhanced MTU3 for motor control, but no Ethernet MAC or GLCDC. | Optimized for servo drives and inverters; lacks connectivity features needed for gateway/HMI use cases. | Choose only for high-performance motor control where Ethernet, graphics, or SDIO are unnecessary. |
Compared with R5F565N9EGFP#30, R5F565NEGFP#30 offers reduced memory and no dual-bank capability - limiting firmware update flexibility - while R5F566TEGFP#30 trades connectivity and graphics for higher CPU throughput and advanced PWM, making it unsuitable as a drop-in replacement for networked or display-centric applications.
Availability
R5F565N9EGFP#30 is available at Aetrix Electronics and suitable for industrial HMI, secure gateways, energy metering, and smart building controllers requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F565N9EGFP#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX65N Group - including R5F565N9EGFP#30 - was designed for secure, connected industrial edge devices requiring real-time performance, rich connectivity (Ethernet/CAN/SD), and hardware security (TSIP/AES) in extended temperature environments.
FAQ
What is the maximum operating frequency and core type of the R5F565N9EGFP#30?
The R5F565N9EGFP#30 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core implements a Harvard architecture with a 5-stage pipeline, variable-length instructions, and supports 240 DMIPS performance. Its design enables deterministic real-time execution ideal for industrial control and networked applications where timing predictability is critical. The R5F565N9EGFP#30 achieves this performance while maintaining low power consumption through dynamic clock gating and multiple low-power modes.
Does the R5F565N9EGFP#30 support dual-bank flash programming for firmware updates?
Yes, the R5F565N9EGFP#30 supports dual-bank flash architecture with 2 MB of on-chip code flash memory. This allows background programming of one bank while executing code from the other, enabling seamless firmware updates without system interruption. The feature is implemented in hardware and requires no external memory or bootloader complexity. This capability is confirmed in the R01DS0276EJ0240 datasheet and is a key differentiator of the R5F565N9EGFP#30 within the RX65N Group for mission-critical industrial applications.
What peripheral interfaces does the R5F565N9EGFP#30 include for industrial connectivity?
The R5F565N9EGFP#30 integrates Ethernet MAC (10/100 Mbps), two CAN 2.0B channels (ISO 11898-1 compliant), three RSPI, three I²C, 13 SCI channels, QSPI, SD host/slave interfaces, and USB 2.0 full-speed host/function. These interfaces enable robust multi-protocol industrial networking - for example, CAN for fieldbus communication, Ethernet for backbone connectivity, and SDIO for local firmware storage. All are supported in the R5F565N9EGFP#30's 176-pin LFBGA package without requiring external bridge ICs.
How does the R5F565N9EGFP#30 meet IEC 60730 safety requirements?
The R5F565N9EGFP#30 includes dedicated hardware features for IEC 60730 Class B compliance: oscillation-stop detection, CRC calculator (CRCA), independent watchdog timer (IWDT) with windowing, self-diagnostic A/D functionality, and register write protection. These are documented in the R01DS0276EJ0240 datasheet under "Useful functions for IEC60730 compliance." The R5F565N9EGFP#30 leverages these integrated capabilities to reduce software certification effort and simplify functional safety validation for industrial control systems.
What is the package type and pin count of the R5F565N9EGFP#30?
The R5F565N9EGFP#30 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 mm × 24 mm with 0.5 mm ball pitch. It provides 136 general-purpose I/O pins, 19 of which are 5-V tolerant, along with dedicated power, ground, clock, reset, and interface signals. This package is explicitly listed in the R01DS0276EJ0240 datasheet as the mechanical form for the R5F565N9EGFP#30 variant.
R5F565N9EGFP#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N9EGFP#30 FAQ
1.How can I place an order for R5F565N9EGFP#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N9EGFP#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N9EGFP#30 reliable?
The price and inventory of R5F565N9EGFP#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N9EGFP#30 is usually 5 days.
3.What payment methods are accepted for R5F565N9EGFP#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N9EGFP#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N9EGFP#30?
R5F565N9EGFP#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N9EGFP#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N9EGFP#30?
For technical support, including R5F565N9EGFP#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N9EGFP#30 requirements.
6.How does Aetrix verify that R5F565N9EGFP#30 is sourced from the original manufacturer or authorized distributors?
All R5F565N9EGFP#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N9EGFP#30 meets industry standards.
7.What is the process for return or replacement of R5F565N9EGFP#30?
All R5F565N9EGFP#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N9EGFP#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N9EGFP#30 part is unused and in its original packaging.
Return procedure for R5F565N9EGFP#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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