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Renesas R5F565N9EGLJ#20
- Part No.:
- R5F565N9EGLJ#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F565N9EGLJ#20.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F565N9EGLJ#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, Ethernet MAC, CAN, SD host/slave, QSPI, and hardware AES-128/192/256 encryption - deployed in industrial HMI, networked gateway, and secure edge node applications.
For engineers reviewing the R5F565N9EGLJ#20 datasheet, R5F565N9EGLJ#20 pinout, R5F565N9EGLJ#20 application, or R5F565N9EGLJ#20 equivalent, key selection criteria include dual-bank flash for safe firmware updates, 136 GPIO with 5-V tolerance, IEEE 802.3-compliant 10/100 Mbps Ethernet with RMII/MII, and IEC60730 safety support including CRC, IWDT, and self-diagnostic A/D.
Technical Context
The R5F565N9EGLJ#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a single-precision IEEE-754 FPU, two MAC units, and a 32-bit multiplier executing in one cycle - all operating at up to 120 MHz with 240 DMIPS throughput.
Its clock system combines external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL for flexible domain partitioning: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/EDMAC/GLCDC, and PCLKB up to 60 MHz for timers and A/D converters - enabling deterministic real-time execution across mixed-criticality peripherals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe bank-swapping during runtime |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion) with zero-wait access at 120 MHz |
| Peripherals | Ethernet MAC (10/100 Mbps, MII/RMII), 2× CAN (ISO 11898-1), SDHI/SDSI, QSPI, 3× RSPI, 13× SCI, 3× RIIC, GLCDC, DRW2D |
| Analog | Two 12-bit A/D units (8 + 21 channels), 2× 12-bit D/A, on-die temperature sensor (±1°C) |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), MPU (8 regions), CRC calculator (8/32-bit), register write protection |
| Package | LFBGA-176 (PLQP0176KB-A), 24 × 24 mm, 0.5-mm pitch, –40°C to +105°C (G-version) |
Pinout & Package
LFBGA-176 package (PLQP0176KB-A) with 136 general-purpose I/O pins, 19 of which are 5-V tolerant, plus dedicated power, ground, clock, reset, debug (JTAG/FINE), and peripheral-specific signal groups (e.g., RMII, SD bus, QSPI, CAN, USB, GLCDC).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Core & I/O power supply / ground | Separate 2.7–3.6 V domains for analog/digital sections; decoupling required per Renesas layout guidelines |
| EXTAL / XTAL | Main crystal oscillator input/output | Supports 8–24 MHz external crystal for precise system timing and Ethernet clock derivation |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and memory configuration at reset release |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MDIO/MDC for PHY register access and link control |
| RMII_RXD0 / RMII_RXD1 / RMII_CRS_DV / RMII_REF_CLK | Ethernet RMII receive signals | Enable 10/100 Mbps operation with minimal pin count; REF_CLK must be 50 MHz ±50 ppm |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | Support 4-bit SD bus at up to 25 MB/s (high-speed mode); includes card detection and write-protect sensing |
| QSPI_IO0–3 / QSPI_SCK / QSPI_SSL | Quad SPI interface | Direct connection to serial NOR flash with single/dual/quad I/O modes; supports XIP and fast read commands |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 FS transceiver | Full-speed (12 Mbps) host/function/OTG operation; integrated transceiver eliminates external PHY |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates without halting application execution - critical for field-deployed gateways and OTA-capable devices |
| IEC60730 safety suite | Includes oscillation-stop detection, CRC calculator (8/32-bit), IWDT with window function, A/D self-diagnostic, and register write protection for Class B compliance |
| Hardware-accelerated graphics | GLCDC + DRW2D engine supports 3-plane overlay, bit blitting, vector drawing, and texture mapping - reduces CPU load in HMI rendering |
| Multi-domain clocking | Independent ICLK (120 MHz), PCLKA (120 MHz), PCLKB (60 MHz), PCLKC/D (60 MHz) domains allow optimized power/performance trade-offs per peripheral group |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - enables deterministic timer-triggered A/D sampling, PWM synchronization, and DMA chaining |
Applications
| Industrial HMI Panel | Smart Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface with LCD display, local data logging, and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Main application processor managing GLCDC, DRW2D, touch controller via SCI/I2C, and Ethernet stack with real-time response to UI events. Use Value: 640 KB SRAM buffers frame data; dual-bank flash allows secure firmware patching; TSIP accelerates TLS handshake for encrypted cloud upload. | Use Scenario: Protocol translator aggregating Modbus RTU, CAN bus, and sensor data into MQTT packets sent over 100 Mbps Ethernet to cloud platform. IC Role / Device Role / Timing Role: Central protocol engine running FreeRTOS, handling concurrent CAN message filtering, SDHI-based local storage, and Ethernet TCP/IP stack. Use Value: 2 MB flash stores multiple protocol stacks; 136 GPIO support isolated RS485/CAN transceivers; RMII interface ensures deterministic packet latency. |
| Secure Edge Node | Networked PLC I/O Module |
Use Scenario: Tamper-resistant field device collecting analog sensor inputs, performing local anomaly detection, and transmitting encrypted telemetry. IC Role / Device Role / Timing Role: Safety-certified controller executing IEC60730 diagnostics, AES-encrypted data packaging, and watchdog-monitored A/D acquisition. Use Value: On-chip TSIP performs AES-256 encryption at line rate; self-diagnostic A/D validates input integrity; IWDT windowing prevents malicious refresh attacks. | Use Scenario: DIN-rail mounted I/O module with digital inputs/outputs, analog current loop outputs, and EtherNet/IP connectivity. IC Role / Device Role / Timing Role: Real-time I/O coordinator using MTU3 PWM for 4–20 mA control, TPU for high-speed counter inputs, and ETHERC for CIP messaging. Use Value: 120 MHz CPU handles CIP object dictionary parsing; PCLKA-synchronized ETHERC/EDMAC ensures <100 µs jitter; 5-V tolerant GPIO interface directly to industrial sensors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEGLJ#20 | Same RX65N Group, identical pinout and peripheral set, but with 1.5 MB code flash and 256 KB SRAM instead of 2 MB/640 KB | Suitable for cost-sensitive designs where full 2 MB flash and 640 KB RAM are not required | Select R5F565NEGLJ#20 when firmware size remains under 1.5 MB and application memory footprint fits within 256 KB SRAM |
| R5F566NHDFP#30 | RX66N Group successor with 160 MHz CPU, 4 MB flash, enhanced TSIP-Lite, and additional CAN FD channel; LQFP-144 package (111 GPIO) | Targeted at next-generation designs requiring higher compute, CAN FD, or larger code space - not pin-compatible | Choose R5F566NHDFP#30 only for new designs needing >120 MHz performance or CAN FD; requires PCB redesign due to different package and pinout |
Compared with R5F565NEGLJ#20, the R5F565N9EGLJ#20 delivers 33% more flash and 150% more SRAM for complex protocol stacks and graphics buffers; versus R5F566NHDFP#30, it offers proven qualification for legacy industrial deployments with no layout change required.
Availability
R5F565N9EGLJ#20 is available at Aetrix Electronics and suitable for industrial HMI, smart gateway, and secure edge node applications requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability validation.
Supply support for R5F565N9EGLJ#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise systems.
The RX65N Group targets high-integrity industrial applications demanding real-time performance, functional safety (IEC60730), rich connectivity (Ethernet/CAN/SD), and hardware security - with R5F565N9EGLJ#20 representing its highest-density LFBGA variant.
FAQ
What is the maximum operating frequency and core type of the R5F565N9EGLJ#20?
The R5F565N9EGLJ#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core features a 5-stage pipeline, Harvard architecture, variable-length instructions, and delivers 240 DMIPS performance. Its design supports ultra-compact code density and deterministic interrupt latency - essential for real-time industrial control tasks executed by the R5F565N9EGLJ#20.
Does the R5F565N9EGLJ#20 support dual-bank flash for safe firmware updates?
Yes, the R5F565N9EGLJ#20 includes a 2 MB on-chip code flash memory with dual-bank architecture. This enables background programming and runtime bank swapping - allowing new firmware to be written to one bank while the application continues executing from the other. This capability is critical for fail-safe field updates in gateways and edge nodes using the R5F565N9EGLJ#20.
What Ethernet interface options does the R5F565N9EGLJ#20 provide?
The R5F565N9EGLJ#20 integrates an IEEE 802.3-compliant Ethernet MAC supporting both MII and RMII physical layer interfaces at 10/100 Mbps. It includes an associated EDMAC with 2 KB transmit/receive FIFOs and supports Magic Packet™ wake-on-LAN. The RMII interface requires a precise 50 MHz reference clock and is commonly used to minimize pin count in compact industrial designs based on the R5F565N9EGLJ#20.
How many analog-to-digital converter channels does the R5F565N9EGLJ#20 have, and what resolution is supported?
The R5F565N9EGLJ#20 integrates two independent 12-bit A/D converter units: S12AD unit 0 with 8 input channels and unit 1 with 21 input channels. Resolution is software-selectable at 8-, 10-, or 12-bit levels. Conversion time is 0.48 µs per channel at full 12-bit resolution. Both units support self-diagnostic functions and analog input disconnection detection - key features for sensor monitoring in systems built around the R5F565N9EGLJ#20.
Is the R5F565N9EGLJ#20 qualified for industrial temperature range and safety standards?
Yes, the R5F565N9EGLJ#20 is rated for the industrial temperature range of –40°C to +105°C (G-version) and includes hardware features supporting IEC60730 Class B compliance: oscillation-stop detection, CRC calculator (8/32-bit), independent watchdog timer (IWDT) with window function, A/D self-diagnostic, and register write protection. These capabilities are documented in the R5F565N9EGLJ#20 datasheet and enable certified safety operation in demanding environments.
R5F565N9EGLJ#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N9EGLJ#20 FAQ
1.How can I place an order for R5F565N9EGLJ#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N9EGLJ#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N9EGLJ#20 reliable?
The price and inventory of R5F565N9EGLJ#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N9EGLJ#20 is usually 5 days.
3.What payment methods are accepted for R5F565N9EGLJ#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N9EGLJ#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N9EGLJ#20?
R5F565N9EGLJ#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N9EGLJ#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N9EGLJ#20?
For technical support, including R5F565N9EGLJ#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N9EGLJ#20 requirements.
6.How does Aetrix verify that R5F565N9EGLJ#20 is sourced from the original manufacturer or authorized distributors?
All R5F565N9EGLJ#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N9EGLJ#20 meets industry standards.
7.What is the process for return or replacement of R5F565N9EGLJ#20?
All R5F565N9EGLJ#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N9EGLJ#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N9EGLJ#20 part is unused and in its original packaging.
Return procedure for R5F565N9EGLJ#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565N9EGLJ#20 Tags
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