Renesas R5F565N9FDFP#10
- Part No.:
- R5F565N9FDFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N9FDFP#10.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,997
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Product details
Overview
R5F565N9FDFP#10 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 2 MB on-chip code flash, 640 KB SRAM, single-precision IEEE-754 FPU, Ethernet MAC, dual CAN 2.0B channels, SD host/slave interfaces, and hardware AES-128/192/256 encryption. It targets industrial HMI, networked gateways, and secure IoT edge controllers requiring real-time processing, connectivity, and functional safety support.
For engineers reviewing the R5F565N9FDFP#10 datasheet, R5F565N9FDFP#10 pinout, R5F565N9FDFP#10 application, or R5F565N9FDFP#10 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), 120-MHz deterministic timing, dual-bank flash for safe firmware updates, integrated GLCDC + DRW2D for embedded graphics, and IEC60730-compliant self-test features including CRC, IWDT, and A/D diagnostic modes.
Technical Context
The R5F565N9FDFP#10 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a memory protection unit (MPU) with eight configurable regions and Trusted Memory (TM) for secure code execution in designated flash banks.
Its clock system combines external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and PLL to generate independent clocks: ICLK (up to 120 MHz for CPU), PCLKA (up to 120 MHz for ETHERC/EDMAC/AES/GLCDC), and PCLKB (up to 60 MHz for most peripherals). The S12AD units operate on dedicated PCLKC/PCLKD clocks for precise analog timing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe bank-swapping during runtime |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| FPU | Single-precision IEEE-754 compliant floating-point unit supporting 32-bit operations |
| Connectivity | Ethernet MAC (10/100 Mbps MII/RMII), 2× CAN 2.0B (32 mailboxes/channel), SDHI/SDSI/MMCIF, QSPI, 3× RSPI, 13× SCI, 3× RIIC |
| Analog Peripherals | Two 12-bit A/D converters (8+21 channels), 2× 12-bit D/A outputs, on-die temperature sensor (±1°C) |
| Security | AES-128/192/256 engine + TSIP module; MPU, TM, register write protection, CRCA, and IEC60730 diagnostics |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +85°C (D-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital/analog domains enable noise isolation; AVCC1 powers S12AD unit 1 and R12DA |
| RES# | Active-low reset input | Asynchronous hardware reset; triggers POR, LVD, and deep software standby release |
| EXTAL / XTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for high-accuracy system clock generation |
| EXCLK | External clock input | Alternative clock source bypassing crystal; enables direct connection to precision oscillator |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and single-chip vs extended ROM configuration at power-on |
| VBATT | Battery backup supply | Provides power to RTC during main VCC dropout; enables calendar retention without external capacitor |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates via bank swap without halting real-time operation |
| Integrated GLCDC + DRW2D | Hardware-accelerated LCD control and 2D graphics rendering eliminate CPU overhead for HMI display tasks |
| IEC60730-compliant safety suite | Includes oscillation-stop detection, CRC calculator, IWDT windowing, A/D self-diagnostic, and register lock bits |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention-e.g., TPU trigger → A/D conversion start → DMA transfer |
| Flexible clock domain partitioning | Independent ICLK, PCLKA–D, FCLK, BCLK allow optimized power/performance trade-offs per peripheral group |
Applications
| Industrial HMI Panel | Secure Gateway Controller |
|---|---|
Use Scenario: Embedded touch-screen interface for PLC-based machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving 480×272 TFT via GLCDC, managing USB/Ethernet comms, and performing real-time motion control loops. Use Value: Integrated DRW2D accelerates UI redraws; dual CAN handles fieldbus bridging; 2 MB flash stores firmware + localized web server assets. | Use Scenario: Edge node aggregating Modbus RTU, CANopen, and BACnet MS/TP traffic into encrypted TLS tunnels over Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Secure protocol translator with hardware AES acceleration, dual Ethernet MAC (host + device), and watchdog-managed failover between primary/backup networks. Use Value: TSIP + AES offloads crypto from CPU; dual-bank flash allows OTA updates without service interruption; ELC synchronizes packet capture → encryption → transmit. |
| Networked Energy Meter | Medical Device Controller |
Use Scenario: DIN-rail mounted smart meter with pulse counting, harmonic analysis, and DLMS/COSEM over TCP/IP. IC Role / Device Role / Timing Role: High-precision measurement controller using S12AD with simultaneous sampling, FFT computation on FPU, and time-stamped event logging to data flash. Use Value: 12-bit A/D with self-diagnostic ensures metrology compliance; RTC with battery backup maintains billing timestamps; 640 KB SRAM buffers waveform samples before compression. | Use Scenario: Portable infusion pump with motor control, pressure sensing, touchscreen GUI, and wireless telemetry. IC Role / Device Role / Timing Role: Safety-critical controller executing IEC62304 Class C software, monitoring analog sensors via A/D, driving stepper motors via MTU3 PWM, and validating UI inputs via MPU-protected code. Use Value: MPU enforces memory isolation between safety and non-safety partitions; IWDT windowing prevents silent failures; temperature sensor monitors SoC thermal margin during motor bursts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#10 | Same RX65N Group, identical 176-pin LFBGA package, but with 1.5 MB flash and 256 KB SRAM (not 640 KB) | Suitable for cost-sensitive designs where full 2 MB flash and expanded RAM are unnecessary | Select when firmware size < 1.5 MB and graphics/data buffering requirements fit within 256 KB SRAM |
| R5F566NHDFP#10 | RX66N Group successor: higher 160 MHz max frequency, enhanced TSIP-Lite, larger 3 MB flash, but no SD slave interface or GLCDC | Targets next-gen applications needing higher compute throughput but less legacy peripheral compatibility | Choose for new designs prioritizing performance headroom and security over backward-compatible display/SDIO support |
Compared with R5F565N9FDFP#10, R5F565NEHDFP#10 reduces memory capacity while maintaining pinout and peripheral set, whereas R5F566NHDFP#10 trades SD slave and GLCDC for higher CPU speed and advanced cryptography-making the R5F565N9FDFP#10 optimal for established HMI and gateway platforms requiring full feature parity.
Availability
R5F565N9FDFP#10 is available at Aetrix Electronics and suitable for industrial HMI, secure gateways, energy metering, and medical device controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F565N9FDFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX65N Group-including R5F565N9FDFP#10-is designed for high-integration industrial and IoT edge devices requiring real-time performance, rich connectivity (Ethernet/CAN/SD), embedded graphics, and functional safety certification support.
FAQ
What is the maximum operating frequency and core type of the R5F565N9FDFP#10?
The R5F565N9FDFP#10 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a 5-stage pipeline, Harvard architecture, and support for variable-length instructions. Its design enables deterministic real-time execution critical for industrial control and communication stacks, and the R5F565N9FDFP#10 maintains this specification across its full industrial temperature range (–40°C to +85°C).
Does the R5F565N9FDFP#10 support secure firmware updates and cryptographic operations?
Yes, the R5F565N9FDFP#10 supports secure firmware updates via its dual-bank flash architecture, allowing background programming and bank-swapping without interrupting application execution. It also integrates hardware AES-128/192/256 encryption and the Trusted Secure IP (TSIP) module for key management and secure boot. These capabilities are fully implemented in the R5F565N9FDFP#10 silicon and documented in the R01DS0276EJ0240 datasheet.
What display and graphics peripherals are integrated into the R5F565N9FDFP#10?
The R5F565N9FDFP#10 integrates a Graphic-LCD Controller (GLCDC) supporting multiple panel types and color depths, plus a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing, bit blitting, and texture mapping. These peripherals operate independently of the CPU, enabling smooth UI rendering in resource-constrained HMI applications. Both modules are present and functional in the R5F565N9FDFP#10, as confirmed by the RX65N Group datasheet revision 2.40.
How many CAN channels does the R5F565N9FDFP#10 support, and what is their compliance level?
The R5F565N9FDFP#10 supports two independent CAN 2.0B channels, each with 32 mailboxes and full compliance with ISO 11898-1. These channels operate concurrently and support both standard and extended frame formats. This dual-CAN capability is explicitly specified for the R5F565N9FDFP#10 in Table 1.2 of the R01DS0276EJ0240 datasheet and is validated across all 176-pin RX65N variants.
What is the package type and pin count of the R5F565N9FDFP#10?
The R5F565N9FDFP#10 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 × 24 mm with 0.5-mm ball pitch. This package is rated for industrial temperature range (–40°C to +85°C) and is mechanically and electrically identical to other 176-pin RX65N MCUs. Pin compatibility and thermal characteristics are fully defined in the R5F565N9FDFP#10's official packaging documentation.
R5F565N9FDFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N9FDFP#10 FAQ
1.How can I place an order for R5F565N9FDFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N9FDFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N9FDFP#10 reliable?
The price and inventory of R5F565N9FDFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N9FDFP#10 is usually 5 days.
3.What payment methods are accepted for R5F565N9FDFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N9FDFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N9FDFP#10?
R5F565N9FDFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N9FDFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N9FDFP#10?
For technical support, including R5F565N9FDFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N9FDFP#10 requirements.
6.How does Aetrix verify that R5F565N9FDFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N9FDFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N9FDFP#10 meets industry standards.
7.What is the process for return or replacement of R5F565N9FDFP#10?
All R5F565N9FDFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N9FDFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N9FDFP#10 part is unused and in its original packaging.
Return procedure for R5F565N9FDFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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