Renesas R5F565N9FGFP#10
- Part No.:
- R5F565N9FGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N9FGFP#10.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,715
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Product details
Overview
R5F565N9FGFP#10 from Renesas is a 32-bit RXv2 core microcontroller operating at up to 120 MHz (240 DMIPS), featuring 2 MB on-chip code flash, 640 KB SRAM, single-precision IEEE-754 FPU, Ethernet MAC, dual CAN channels, SD host/slave interfaces, and hardware AES/TSIP encryption. It targets industrial HMI, networked gateways, and secure IoT edge controllers requiring real-time processing, connectivity, and functional safety support.
For engineers reviewing the R5F565N9FGFP#10 datasheet, R5F565N9FGFP#10 pinout, R5F565N9FGFP#10 application, or R5F565N9FGFP#10 equivalent, key selection criteria include its 176-pin LFBGA package, 120-MHz deterministic timing, dual-bank flash for safe firmware updates, integrated GLCDC+DRW2D for graphics acceleration, and IEC60730-compliant self-test features including CRC, IWDT, and A/D diagnostic modes.
Technical Context
The R5F565N9FGFP#10 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling ultra-compact code density. Its memory subsystem includes dual-bank 2-MB flash supporting background programming and bank-swapping during execution, plus 640 KB of zero-wait-state SRAM partitioned into 256 KB main RAM and 384 KB expansion RAM.
Peripheral integration centers on deterministic real-time control and secure connectivity: the ETHERC/EDMAC supports 10/100 Mbps MII/RMII with wake-on-LAN; two ISO 11898-1 CAN channels each provide 32 mailboxes; and the S12AD unit 1 delivers 21-channel 12-bit A/D conversion with per-channel sampling time control and disconnection detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB dual-bank code flash; enables safe over-the-air updates without halting execution |
| SRAM | 640 KB total (256 KB + 384 KB expansion); zero-wait access at 120 MHz |
| FPU | Single-precision IEEE-754 compliant; accelerates motor control, sensor fusion, and filtering |
| Connectivity | Ethernet MAC + EDMAC, 2× CAN, 3× RSPI, 2× SCIi (16-byte FIFO), QSPI, SDHI/SDSI, MMCIF |
| Analog Peripherals | 2× 12-bit S12AD (8+21 ch), 2× R12DA, on-die temperature sensor (±1°C) |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), MPU, CRC calculator, register write protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +105°C (G-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate analog/digital domains enable noise isolation for ADC/DAC operation |
| XTAL, EXTAL | Main clock oscillator terminals | Supports 8–24 MHz crystal for precise system timing and Ethernet PHY synchronization |
| ETH_MDC, ETH_MDIO | MDIO management interface | Enables runtime configuration and status polling of external Ethernet PHY devices |
| CAN0_TX, CAN0_RX | Channel 0 differential CAN bus interface | Direct connection to ISO 11898-1 transceiver; supports standard/extended frames and 32-mailbox FIFO |
| SD0_CMD, SD0_CLK, SD0_DAT0–3 | 4-bit SD host interface signals | Hardware-accelerated SD memory card interface supporting high-speed mode (25 MB/s) |
| GLCD_D0–23, GLCD_DE, GLCD_HS, GLCD_VS | Graphic LCD controller parallel output | Drives 24-bit RGB TFT panels up to WXGA resolution with hardware alpha blending across 3 layers |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with BGO | Enables seamless firmware updates: new code writes to inactive bank while active bank executes |
| IEC60730-compliant diagnostics | Integrated CRCA, IWDT windowing, A/D self-test voltages, and register write protection meet Class B requirements |
| GLCDC + DRW2D co-processor | Offloads GUI rendering: 2D vector drawing, bit blitting, texture mapping, and display list execution without CPU intervention |
| Event Link Controller (ELC) | Hardware interconnect for 83 internal events eliminates software overhead in timer-triggered ADC conversions or PWM sync |
| Secure boot via Trusted Memory | TM function restricts instruction fetch to protected flash regions, preventing unauthorized code execution |
Applications
| Industrial HMI Panel | Smart Energy Gateway |
|---|---|
Use Scenario: Touch-enabled factory operator interface with real-time alarm visualization and local data logging. IC Role / Device Role / Timing Role: Primary application processor managing GLCDC-driven TFT display, touch controller SPI, and EtherCAT-over-Ethernet communication stack. Use Value: DRW2D hardware acceleration renders animated gauges at 60 fps; dual CAN handles legacy PLC fieldbus bridging; TSIP secures firmware OTA updates. | Use Scenario: DIN-rail mounted gateway aggregating metering data from Modbus RTU, M-Bus, and DLMS/COSEM endpoints. IC Role / Device Role / Timing Role: Central protocol translator with Ethernet backhaul, dual CAN for substation SCADA, and SDHI for local event log storage. Use Value: 2 MB flash stores multiple protocol stacks; 640 KB SRAM buffers concurrent TLS sessions; IEC60730 diagnostics ensure certification compliance. |
| Secure IoT Edge Node | Networked Building Controller |
Use Scenario: Wireless-connected HVAC controller performing local PID loop closure and encrypted cloud telemetry upload. IC Role / Device Role / Timing Role: Real-time control MCU executing 1-ms control loops via MTU3 PWM outputs while running TLS 1.2 on AES engine. Use Value: Hardware AES-256 reduces TLS handshake latency by >70%; on-die temperature sensor feeds thermal derating logic; RTC with battery backup maintains schedule integrity. | Use Scenario: BACnet/IP-enabled lighting and HVAC controller with embedded web server and local scheduling. IC Role / Device Role / Timing Role: Full-stack network processor handling TCP/IP stack, BACnet MS/TP bridging via CAN, and SD slave interface for removable configuration cards. Use Value: Integrated Ethernet MAC + PHY interface eliminates external PHY BOM; SD slave interface enables field-configurable parameter loading; 120-MHz core sustains 100+ concurrent BACnet objects. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEBDFP#30 | Same RX65N Group, 144-pin LQFP, 1 MB flash, 256 KB SRAM, no Ethernet MAC | Suitable for cost-sensitive CAN/USB-only edge nodes without LAN connectivity | Select when Ethernet is unnecessary and PCB layout favors QFP over BGA |
| R7FA6M2AF3CFP#AA0 | RX72M Group, 176-pin LFBGA, 120 MHz, 2 MB flash, but adds USB HS, 2× EtherCAT slaves, no TSIP | Targeted at motion control with synchronized multi-axis servo drives | Choose for EtherCAT real-time networking; avoid if cryptographic security (TSIP) is mandatory |
Compared with R5F565N9FGFP#10, the R5F565NEBDFP#30 sacrifices Ethernet and half the memory for lower cost and simpler packaging, while the R7FA6M2AF3CFP#AA0 trades TSIP-based security for EtherCAT timing precision-making R5F565N9FGFP#10 optimal for secure, graphics-rich, Ethernet-connected industrial edge devices.
Availability
R5F565N9FGFP#10 is available at Aetrix Electronics and suitable for industrial HMIs, smart energy gateways, and secure IoT edge controllers requiring stable component supply, long-term lifecycle assurance, and automotive-grade temperature resilience.
Supply support for R5F565N9FGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.
The RX65N Group-including R5F565N9FGFP#10-is designed for industrial human-machine interfaces and networked edge controllers requiring integrated graphics, secure connectivity, functional safety compliance, and deterministic real-time performance.
FAQ
What is the maximum operating frequency and core type of the R5F565N9FGFP#10?
The R5F565N9FGFP#10 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, multiplier, divider, and memory protection unit. Its CISC Harvard architecture with 5-stage pipeline ensures deterministic real-time behavior critical for industrial control applications where the R5F565N9FGFP#10 is deployed.
Does the R5F565N9FGFP#10 support secure firmware updates and cryptographic operations?
Yes, the R5F565N9FGFP#10 integrates AES-128/192/256 encryption engines and the Trusted Secure IP (TSIP) module for key management and secure boot. Its dual-bank flash memory supports background programming (BGO), enabling safe over-the-air firmware updates without interrupting execution. The Trusted Memory (TM) function prevents unauthorized read access to protected code regions-key capabilities that make the R5F565N9FGFP#10 suitable for certified IEC60730 Class B applications requiring tamper resistance and update integrity.
What graphics and display capabilities does the R5F565N9FGFP#10 provide?
The R5F565N9FGFP#10 includes a dedicated Graphic-LCD Controller (GLCDC) supporting 24-bit RGB TFT panels up to WXGA resolution, and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector graphics, bit blitting, texture mapping, and display list execution. These peripherals operate independently of the CPU, enabling smooth GUI rendering at 60 fps. This integrated graphics subsystem makes the R5F565N9FGFP#10 ideal for industrial HMIs where low-latency visual feedback and rich user interfaces are required without burdening the main application core.
How many CAN channels and Ethernet interfaces does the R5F565N9FGFP#10 integrate?
The R5F565N9FGFP#10 integrates two independent CAN 2.0B-compliant channels (ISO 11898-1), each with 32 message mailboxes, and a full-featured Ethernet MAC controller supporting 10/100 Mbps in MII or RMII mode-including wake-on-LAN and IEEE 802.3x flow control. An associated EDMAC handles descriptor-based DMA transfers with 2 KB transmit/receive FIFOs. This combination allows the R5F565N9FGFP#10 to serve as a robust protocol gateway bridging CAN field networks to Ethernet backbones in industrial automation systems.
What is the package type and temperature grade of the R5F565N9FGFP#10?
The R5F565N9FGFP#10 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 × 24 mm with 0.5-mm ball pitch. It is rated for the G-version industrial temperature range of –40°C to +105°C, making it suitable for deployment in harsh environments such as factory floors, outdoor energy infrastructure, and transportation systems. This package and rating are explicitly confirmed in the R01DS0276EJ0240 datasheet for the R5F565N9FGFP#10 device.
R5F565N9FGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N9FGFP#10 FAQ
1.How can I place an order for R5F565N9FGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N9FGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N9FGFP#10 reliable?
The price and inventory of R5F565N9FGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N9FGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F565N9FGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N9FGFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565N9FGFP#10?
R5F565N9FGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N9FGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N9FGFP#10?
For technical support, including R5F565N9FGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N9FGFP#10 requirements.
6.How does Aetrix verify that R5F565N9FGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F565N9FGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N9FGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F565N9FGFP#10?
All R5F565N9FGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N9FGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N9FGFP#10 part is unused and in its original packaging.
Return procedure for R5F565N9FGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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