Renesas R5F565N9FGFP#30
- Part No.:
- R5F565N9FGFP#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565N9FGFP#30.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:270
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Product details
Overview
R5F565N9FGFP#30 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, and GLCDC/DRW2D graphics subsystems - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F565N9FGFP#30 datasheet, R5F565N9FGFP#30 pinout, R5F565N9FGFP#30 application, or R5F565N9FGFP#30 equivalent, this MCU delivers deterministic real-time control with IEC60730 safety support, hardware AES-128/192/256 encryption, and dual-bank flash for safe firmware updates - critical for field-deployed embedded systems requiring functional safety and secure boot.
Technical Context
The R5F565N9FGFP#30 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates a memory protection unit (MPU) supporting eight configurable regions and Trusted Memory (TM) to restrict instruction fetches from protected flash areas - essential for secure firmware execution.
Clocking is managed via multiple sources: external crystal (8–24 MHz), internal HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator (120 kHz). Peripheral clocks are independently configurable - PCLKA up to 120 MHz for ETHERC/EDMAC/AES/GLCDC/DRW2D, PCLKB up to 60 MHz for most timers and ADCs - enabling precise power/performance trade-offs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz - enables high-throughput deterministic control without external co-processors. |
| Flash Memory | 2 MB code flash with dual-bank structure - supports background programming and zero-downtime firmware updates via bank swap. |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), no wait states @ 120 MHz - eliminates external RAM for complex real-time tasks. |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), 2-channel 12-bit D/A, on-die temperature sensor (±1°C) - enables local sensor fusion and closed-loop analog control. |
| Connectivity | Ethernet MAC (10/100 Mbps MII/RMII), 2x CAN (ISO11898-1), 3x RSPI, 1x QSPI, 3x I²C (1 Mbps), 13x SCI - supports multi-protocol industrial networking. |
| Graphics & Media | Graphic-LCD controller (GLCDC) + 2D drawing engine (DRW2D) - renders UIs directly to RGB/TFT panels without GPU offload. |
| Security | AES-128/192/256, Trusted Secure IP (TSIP), CRC calculator (8/32-bit), register write protection - meets IEC60730 Class B and secure boot requirements. |
Pinout & Package
Package: PLQP0176KB-A (176-pin LQFP, 24 × 24 mm, 0.5-mm pitch, –40°C to +105°C operating range).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital (VCC), analog unit 0 (AVCC0), and analog unit 1 (AVCC1) rails - enable noise isolation for precision ADC/DAC operation. |
| XTAL / EXTAL | Main clock oscillator terminals | Supports 8–24 MHz crystal resonator - provides stable timing source for Ethernet, USB, and RTC synchronization. |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC bus - allows configuration of external PHY without GPIO bit-banging. |
| TXD0 / RXD0 | SCI0 asynchronous serial interface | Full-duplex UART pins with programmable baud rate generator - used for debug console or host communication. |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s) - enables direct attachment of SD cards for data logging or firmware storage. |
| USB_VBUS / USB_D+ / USB_D− | USB 2.0 Full-Speed transceiver | Integrated PHY with 2 KB on-chip buffer - supports host/function/OTG without external transceiver or pull-up resistors. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed - eliminates system downtime during field upgrades. |
| Trusted Memory (TM) function | Restricts CPU instruction fetches to designated flash regions - prevents unauthorized code execution and enforces secure boot chain integrity. |
| Event Link Controller (ELC) | Hardware interconnect for 83 internal events - eliminates CPU polling/interrupt latency for timer-triggered ADC sampling or PWM waveform generation. |
| IEC60730 safety support | Includes oscillation-stop detection, CRC calculator, self-diagnostic A/D, IWDT windowing, and register write protection - reduces certification effort for Class B applications. |
| GLCDC + DRW2D graphics subsystem | Hardware-accelerated 2D rendering and LCD panel driving - offloads CPU from pixel manipulation and enables responsive GUIs on resource-constrained edge devices. |
Applications
| Industrial HMI Panel | Secure Network Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time status visualization and alarm logging. IC Role / Device Role / Timing Role: Primary application processor executing RTOS, driving TFT LCD via GLCDC, managing touch input via SCI/USB, and communicating over CAN/Ethernet. Use Value: Integrated DRW2D accelerates bitmap scaling and alpha blending; dual-bank flash ensures safe OTA updates without halting machine operation. | Use Scenario: Protocol translation bridge connecting legacy Modbus RTU field devices to cloud-based SCADA via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Central protocol stack processor handling concurrent CAN, RS485 (SCI), Ethernet, and SD card logging - with hardware AES for encrypted telemetry upload. Use Value: On-chip Ethernet MAC + dual CAN + multiple SCI channels eliminate external protocol ICs; TSIP accelerates TLS handshake for secure MQTT. |
| Smart Energy Meter | Medical Edge Sensor Hub |
Use Scenario: DIN-rail mounted meter aggregating current/voltage readings from CT sensors and transmitting via NB-IoT backhaul. IC Role / Device Role / Timing Role: Real-time data acquisition controller running IEC60730-compliant diagnostics, performing RMS calculations via FPU, and managing secure firmware updates. Use Value: Hardware CRC and IWDT windowing satisfy Class B safety requirements; 12-bit dual A/D achieves <1% THD measurement accuracy at 120 MSPS effective sample rate. | Use Scenario: Portable patient monitor collecting ECG, SpO₂, and temperature data, displaying waveforms locally and uploading to hospital EMR via Wi-Fi. IC Role / Device Role / Timing Role: Multi-sensor fusion hub with simultaneous analog acquisition (S12AD), real-time waveform rendering (DRW2D), and encrypted data transmission (AES + TLS). Use Value: On-die temperature sensor calibrates analog front-end drift; standby RAM preserves context during low-power sleep between measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEBDFP#30 | Same RX65N family, 176-pin LQFP, but with 1 MB flash and 256 KB SRAM - lacks dual-bank flash and DRW2D graphics engine. | Suitable for cost-sensitive gateways without local GUI or field-upgradable firmware requirements. | Select when full 2 MB flash, dual-bank update capability, and hardware graphics acceleration are not required. |
| R7FA6M2AF3CFP#AA0 | RX72M-series successor: higher 240 MHz CPU, enhanced EtherCAT support, but no integrated SD host/slave or GLCDC - different peripheral set and package (176-pin LQFP same footprint). | Better suited for motion control with real-time Ethernet, less optimal for HMI-centric designs requiring local display rendering. | Choose for next-gen designs needing higher compute throughput and industrial Ethernet protocols, accepting trade-off in graphics and SD functionality. |
Compared with R5F565N9FGFP#30, R5F565NEBDFP#30 reduces memory and graphics capability for lower BOM cost, while R7FA6M2AF3CFP#AA0 shifts focus toward motion control with higher CPU performance but removes integrated SD and LCD subsystems - making R5F565N9FGFP#30 uniquely balanced for secure, graphics-enabled industrial edge nodes.
Availability
R5F565N9FGFP#30 is available at Aetrix Electronics and suitable for industrial HMI, secure network gateways, and smart energy metering requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for R5F565N9FGFP#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX65N Group - including R5F565N9FGFP#30 - was designed for secure, graphics-capable industrial edge applications demanding functional safety, encrypted communications, and rich human-machine interaction without external graphics processors.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565N9FGFP#30?
The R5F565N9FGFP#30 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core with Harvard architecture and 5-stage pipeline. It delivers 240 DMIPS performance and includes single-precision IEEE-754 floating-point unit (FPU), two multiply-and-accumulate units, and 32-bit multiplier with one-cycle execution - enabling high-efficiency signal processing and real-time control in the R5F565N9FGFP#30.
Does the R5F565N9FGFP#30 support secure firmware updates and cryptographic operations?
Yes, the R5F565N9FGFP#30 supports secure firmware updates via its dual-bank flash architecture, allowing background programming while executing from the active bank. It also integrates AES-128/192/256 encryption engines, Trusted Secure IP (TSIP), CRC calculator (8/32-bit), and register write protection - all verified in the R01DS0276EJ0240 datasheet to meet IEC60730 Class B requirements for the R5F565N9FGFP#30.
What display and graphics capabilities does the R5F565N9FGFP#30 provide?
The R5F565N9FGFP#30 integrates a Graphic-LCD Controller (GLCDC) supporting RGB/TFT panels and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing, bit blitting, rotation, and scaling. It supports 32-/16-bpp graphics, CLUT formats, and display list rendering - eliminating need for external GPU in HMI applications. This full graphics subsystem is confirmed for the R5F565N9FGFP#30 in the RX65N Group datasheet Rev.2.40.
Which communication interfaces are integrated into the R5F565N9FGFP#30?
The R5F565N9FGFP#30 integrates Ethernet MAC (10/100 Mbps MII/RMII), two CAN 2.0B channels (ISO11898-1), three RSPI, one QSPI, three I²C (up to 1 Mbps), 13 SCI channels (asynchronous/smart-card/SPI/I²C modes), SD host/slave, MMCIF, and USB 2.0 FS host/function/OTG - all documented in the R01DS0276EJ0240 datasheet for the R5F565N9FGFP#30.
What is the package type and temperature grade of the R5F565N9FGFP#30?
The R5F565N9FGFP#30 uses the PLQP0176KB-A package: 176-pin LQFP, 24 × 24 mm body, 0.5-mm pitch, and is rated for –40°C to +105°C (G-version). This industrial-grade thermal specification and pin-compatible footprint with other RX65N 176-pin variants is explicitly listed in the "Package Information" section of the R01DS0276EJ0240 datasheet for the R5F565N9FGFP#30.
R5F565N9FGFP#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565N9FGFP#30 FAQ
1.How can I place an order for R5F565N9FGFP#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565N9FGFP#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565N9FGFP#30 reliable?
The price and inventory of R5F565N9FGFP#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565N9FGFP#30 is usually 5 days.
3.What payment methods are accepted for R5F565N9FGFP#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565N9FGFP#30 transactions.
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R5F565N9FGFP#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565N9FGFP#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565N9FGFP#30?
For technical support, including R5F565N9FGFP#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565N9FGFP#30 requirements.
6.How does Aetrix verify that R5F565N9FGFP#30 is sourced from the original manufacturer or authorized distributors?
All R5F565N9FGFP#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565N9FGFP#30 meets industry standards.
7.What is the process for return or replacement of R5F565N9FGFP#30?
All R5F565N9FGFP#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565N9FGFP#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565N9FGFP#30 part is unused and in its original packaging.
Return procedure for R5F565N9FGFP#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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