Renesas R5F565N9FGLK#20

Overview

R5F565N9FGLK#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with on-chip FPU, 240 DMIPS performance, 2-MB code flash (dual-bank), 640-KB SRAM, Ethernet MAC, CAN, SD host/slave, QSPI, and hardware AES-128/192/256 encryption - deployed in industrial HMIs, networked PLCs, and secure IoT gateways.

For engineers reviewing the R5F565N9FGLK#20 datasheet, R5F565N9FGLK#20 pinout, R5F565N9FGLK#20 application, or R5F565N9FGLK#20 equivalent, key selection criteria include its 176-pin LFBGA package, -40°C to +105°C operating range (G-version), integrated GLCDC + DRW2D for graphics acceleration, and TSIP-based secure boot capability.

Technical Context

The R5F565N9FGLK#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and IEEE-754 single-precision FPU - enabling deterministic real-time control at 120 MHz. It integrates dual-bank flash for safe firmware updates and supports simultaneous execution and programming via background operations (BGO).

Its peripheral set includes an Ethernet MAC with RMII/MII support, two CAN 2.0B channels (32 mailboxes each), 13 SCI channels (including FIFO-equipped SCIi), and dedicated security modules: TSIP for key management and CRCA for CRC-32/8 computation - all synchronized across four independent clock domains (ICLK, PCLKA–D).

Key Specifications

Pinout & Package

Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm body, 0.5-mm ball pitch, 136 general-purpose I/O pins (5-V tolerant on 19 pins), 1 dedicated IRQ input, and configurable pull-up/open-drain outputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit industrial MCU applications.

Compared with R5F565N9FGLK#20, the R5F565NEHDFP#30 offers reduced peripheral integration and thermal grade for cost-constrained applications, while the R7FA6M2AF3CFP#AA0 trades networking and security for higher PWM precision and motor-control timing - neither matches the full feature set of the R5F565N9FGLK#20 in secure, graphics-rich, connected industrial systems.

Availability

R5F565N9FGLK#20 is available at Aetrix Electronics and suitable for industrial HMIs, networked PLCs, and secure IoT gateways requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for R5F565N9FGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and infrastructure markets.

The RX65N Group - including R5F565N9FGLK#20 - was designed for secure, graphics-capable industrial edge devices requiring real-time control, multiple fieldbuses, and hardware-enforced trust anchors.

FAQ

What is the maximum operating frequency and core type of the R5F565N9FGLK#20?

The R5F565N9FGLK#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, 5-stage pipeline, and Harvard architecture - optimized for deterministic real-time execution in industrial control applications.

Does the R5F565N9FGLK#20 support secure boot and cryptographic acceleration?

Yes, the R5F565N9FGLK#20 integrates Trusted Secure IP (TSIP) for hardware-accelerated AES-128/192/256, SHA, RSA, and key wrapping. It also includes a memory protection unit (MPU), register write protection, and Trusted Memory (TM) functionality - enabling certified secure boot and runtime firmware integrity verification.

What graphics and display interfaces does the R5F565N9FGLK#20 provide?

The R5F565N9FGLK#20 includes a Graphic-LCD Controller (GLCDC) supporting 3-plane overlay and multiple pixel formats (32/16/8 bpp), plus a 2D Drawing Engine (DRW2D) for bit-blitting, rotation, and vector drawing. These accelerators reduce CPU load in HMI applications and eliminate the need for external graphics ICs.

Which communication interfaces are integrated into the R5F565N9FGLK#20?

The R5F565N9FGLK#20 integrates Ethernet MAC (10/100 Mbps, RMII/MII), two CAN 2.0B channels (32 mailboxes each), 13 SCI channels (including FIFO-equipped SCIi), three I²C interfaces (up to 1 Mbps), three RSPI, one QSPI, SD host/slave, MMCIF, and USB 2.0 FS host/function/OTG - enabling multi-protocol industrial connectivity.

What is the package type and pin count of the R5F565N9FGLK#20?

The R5F565N9FGLK#20 uses the PLQP0176KB-A package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA) with 24 mm × 24 mm body size and 0.5-mm ball pitch. It provides 136 general-purpose I/O pins, 19 of which are 5-V tolerant, and supports industrial temperature range (-40°C to +105°C).