My Inquiry
My Account
Renesas R5F565NCDGBG#20
- Part No.:
- R5F565NCDGBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F565NCDGBG#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 176LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:152
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F565NCDGBG#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with integrated FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, Ethernet MAC, CAN 2.0B, SD host/slave interfaces, and hardware AES-128/192/256 encryption - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F565NCDGBG#20 datasheet, R5F565NCDGBG#20 pinout, R5F565NCDGBG#20 application, or R5F565NCDGBG#20 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C G-grade operation, dual-bank flash for safe firmware updates, 2-channel CAN with 32 mailboxes per channel, and integrated GLCDC+DRW2D for embedded graphics acceleration.
Technical Context
The R5F565NCDGBG#20 implements the RXv2 CPU core with IEEE-754 single-precision FPU, 5-stage CISC Harvard pipeline, and memory protection unit (MPU) supporting eight configurable regions. It integrates dual-clock domain peripherals: PCLKA-synchronized modules (ETHERC, MTU3, GLCDC, DRW2D) run up to 120 MHz, while PCLKB-synchronized modules (S12AD, TMR, CMT) operate up to 60 MHz.
Its real-time subsystem includes a battery-backed RTC with time-capture, independent watchdog timer (IWDT) with window function and dedicated 120-kHz oscillator, and IEC60730-compliant safety features including oscillation-stop detection, CRC calculator (CRCA), and register write protection. The device supports simultaneous Ethernet (MII/RMII), USB 2.0 FS host/function, and SDIO/SD/MMC protocols without external glue logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB code flash with dual-bank structure enabling background programming and safe firmware swap |
| SRAM | 640 KB on-chip SRAM (256 KB main + 384 KB expansion), zero-wait-state access at 120 MHz |
| Operating Temp | G-grade: –40°C to +105°C, qualified for extended industrial environments |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, 136 GPIOs (19 with 5-V tolerance) |
| Peripherals | Ethernet MAC (10/100 Mbps), 2× CAN 2.0B (32 mailboxes/channel), SDHI/SDSI/MMCIF, GLCDC+DRW2D, 2× 12-bit ADC (29 total channels), 2× 12-bit DAC |
| Security | Hardware AES engine (128/192/256-bit keys), Trusted Secure IP (TSIP), MPU, TM protected code area |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm pitch, RoHS-compliant, lead-free, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Separate analog/digital domains; AVCC0/AVCC1 power S12AD units and internal regulators |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin cell or supercapacitor |
| RES# | Active-low reset input | Asynchronous hardware reset; low pulse ≥ 100 ns triggers full system reset |
| EXTAL, XTAL | External crystal oscillator terminals | Supports 8–24 MHz crystal for high-accuracy clock source; enables PLL multiplication to 120 MHz |
| ETH_MDC, ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC bus for PHY configuration and status monitoring |
| ETH_TXD0–3, ETH_RXD0–3, ETH_TX_EN, ETH_RX_ER | Ethernet physical layer signals | Full MII interface; RMII mode uses subset (TXD0/1, TX_EN, RXD0/1, CRS_DV, REF_CLK) |
| USB_DP, USB_DM | USB 2.0 differential data lines | Integrated transceiver supports full-speed (12 Mbps) host/function/OTG; no external PHY required |
| SD0_CMD, SD0_CLK, SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); compatible with SD Memory Card Spec. v3.01 |
| CAN0_TX, CAN0_RX, CAN1_TX, CAN1_RX | CAN transceiver I/O | Direct connection to external CAN transceivers; each channel supports standard/extended frames and 32 mailboxes |
| GLCD_D0–23, GLCD_HSYNC, GLCD_VSYNC, GLCD_DE | Graphic LCD controller outputs | 24-bit RGB parallel interface with timing control; drives TFT panels up to WXGA resolution |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed, eliminating downtime |
| Integrated GLCDC + DRW2D | Hardware-accelerated 2D graphics rendering and LCD timing control - reduces CPU load by >70% vs. software-only rendering |
| IEC60730 Class B support | Includes built-in self-test (BIST) for A/D converter, oscillation-stop detection, CRC calculator, and register lock mechanisms |
| Event Link Controller (ELC) | 83 internal event sources routed without CPU intervention - e.g., TPU output triggers ADC conversion with <100 ns latency |
| Trusted Secure IP (TSIP) | Hardware cryptographic accelerator with key wrapping, secure boot, and tamper-resistant key storage - certified to Common Criteria EAL4+ |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor running RTOS, driving 800×480 TFT via GLCDC, managing CAN bus to field devices, and executing AES-encrypted OTA updates. Use Value: Integrated DRW2D accelerates UI animations; dual-bank flash ensures zero-downtime firmware patches; TSIP secures update integrity. | Use Scenario: Protocol-bridging gateway aggregating Modbus RTU, CANopen, and EtherNet/IP traffic into encrypted TLS tunnels to cloud platforms. IC Role / Device Role / Timing Role: Central protocol translator with Ethernet MAC, dual CAN, RSPI, and hardware crypto - synchronizing time-critical fieldbus cycles via ELC-triggered timers. Use Value: On-chip Ethernet + CAN eliminates external PHY/transceiver BOM; AES engine encrypts payloads at line rate; RTC with time-capture logs event timestamps with µs precision. |
| Networked Energy Meter | Medical Device Controller |
Use Scenario: DIN-rail mounted smart meter with pulse counting, tariff switching, and DLMS/COSEM over TCP/IP. IC Role / Device Role / Timing Role: Real-time metering controller using S12AD for precision voltage/current sampling, Ethernet for utility comms, and SDHI for firmware/configuration storage. Use Value: 12-bit ADC with self-diagnostic meets IEC62053 accuracy requirements; dual-bank flash enables certified firmware rollbacks; 105°C rating supports enclosed cabinet operation. | Use Scenario: Portable diagnostic imaging device requiring low-latency image capture, display, and HIPAA-compliant data export. IC Role / Device Role / Timing Role: Image acquisition and rendering hub: PDC captures CMOS sensor data, DRW2D renders overlays, GLCDC drives display, AES encrypts exported DICOM files. Use Value: Parallel data capture unit acquires 1280×720@30fps without CPU overhead; hardware AES-256 meets NIST SP 800-38A; standby RAM preserves state during battery swaps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFP#30 | Same RX65N Group, 144-pin LFQFP package (PLQP0144KA-B), 111 GPIOs, 1.5 MB flash, 256 KB SRAM | Limited peripheral count (1× CAN, no SD slave), smaller footprint; suited for space-constrained gateways without graphics | Select when board space is critical and GLCDC/DRW2D/SDSI are unnecessary |
| R5F566TNDDB#20 | RX66T Group, 176-pin LFBGA, 160 MHz, FPU, 2 MB flash, but optimized for motor control (3× MTU3, 3× encoder interfaces, no GLCDC/SDSI) | Targeted at servo/inverter drives; lacks Ethernet MAC, SD interfaces, and graphics engines | Select for high-performance motor control where real-time PWM precision outweighs connectivity and display needs |
Compared with R5F565NEDFP#30, the R5F565NCDGBG#20 delivers full peripheral complement and larger memory in the same pin-count package; versus R5F566TNDDB#20, it trades motor-control timing precision for integrated networking, storage, and graphics - making it optimal for connected HMI and gateway roles.
Availability
R5F565NCDGBG#20 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and networked energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for R5F565NCDGBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets, with annual revenue exceeding $10 billion.
The RX65N Group - including R5F565NCDGBG#20 - was designed specifically for secure, connected industrial equipment requiring rich human-machine interaction, deterministic real-time control, and robust cybersecurity at the edge.
FAQ
What is the maximum operating frequency and core type of the R5F565NCDGBG#20?
The R5F565NCDGBG#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core delivers 240 DMIPS performance and includes a single-precision IEEE-754 floating-point unit, 5-stage pipeline, and memory protection unit (MPU). Its instruction set supports DSP operations and ultra-compact code density, making it suitable for demanding real-time industrial applications.
Does the R5F565NCDGBG#20 support dual-bank flash for firmware updates?
Yes, the R5F565NCDGBG#20 includes 2 MB of on-chip code flash memory with a dual-bank structure. This allows background programming of one bank while executing code from the other, enabling safe, zero-downtime firmware updates - a critical requirement for industrial gateways and medical devices where system availability is paramount.
What graphics capabilities does the R5F565NCDGBG#20 provide?
The R5F565NCDGBG#20 integrates a Graphic-LCD Controller (GLCDC) supporting 24-bit RGB parallel output up to WXGA resolution and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing, bit blitting, rotation, and scaling. These blocks offload graphics rendering from the CPU, reducing processing load by over 70% compared to software-only implementations in HMI applications.
Which communication interfaces are included in the R5F565NCDGBG#20 for industrial networking?
The R5F565NCDGBG#20 integrates Ethernet MAC (10/100 Mbps MII/RMII), two CAN 2.0B channels (32 mailboxes each), USB 2.0 FS host/function/OTG, SD host/slave, MMCIF, three RSPI, one QSPI, three I2C, and 13 SCI channels. This comprehensive suite enables protocol bridging between fieldbuses (CANopen, Modbus), wired networks (Ethernet), and removable media (SD cards) without external interface ICs.
How does the R5F565NCDGBG#20 meet IEC60730 safety requirements?
The R5F565NCDGBG#20 includes multiple IEC60730 Class B compliance features: oscillation-stop detection, hardware CRC calculator (CRCA), self-diagnostic A/D converter test, independent watchdog timer (IWDT) with window function, register write protection, and memory protection unit (MPU). These are documented in Renesas' official IEC60730 certification report for the RX65N Group.
R5F565NCDGBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NCDGBG#20 FAQ
1.How can I place an order for R5F565NCDGBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NCDGBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NCDGBG#20 reliable?
The price and inventory of R5F565NCDGBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NCDGBG#20 is usually 5 days.
3.What payment methods are accepted for R5F565NCDGBG#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NCDGBG#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NCDGBG#20?
R5F565NCDGBG#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NCDGBG#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NCDGBG#20?
For technical support, including R5F565NCDGBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NCDGBG#20 requirements.
6.How does Aetrix verify that R5F565NCDGBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NCDGBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NCDGBG#20 meets industry standards.
7.What is the process for return or replacement of R5F565NCDGBG#20?
All R5F565NCDGBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NCDGBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NCDGBG#20 part is unused and in its original packaging.
Return procedure for R5F565NCDGBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565NCDGBG#20 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
