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Renesas R5F565NCDGLC#20
- Part No.:
- R5F565NCDGLC#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 177-TFLGA
- Datasheet:
-
R5F565NCDGLC#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 177TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:239
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Product details
Overview
R5F565NCDGLC#20 from Renesas is a 32-bit RXv2 microcontroller with 120 MHz CPU frequency, 240 DMIPS performance, single-precision IEEE-754 FPU, 2 MB on-chip code flash memory, and 640 KB SRAM. It integrates Ethernet MAC, dual CAN channels, SD host/slave interfaces, QSPI, GLCDC, DRW2D, and hardware AES encryption - designed for industrial HMI, networked gateway, and secure edge node applications.
For engineers reviewing the R5F565NCDGLC#20 datasheet, R5F565NCDGLC#20 pinout, R5F565NCDGLC#20 application, or R5F565NCDGLC#20 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), 120 MHz real-time deterministic execution, dual-bank flash for safe firmware updates, integrated Ethernet PHY support, and IEC60730 safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565NCDGLC#20 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and MPU-based memory protection. It supports little-endian data and instruction layout, with 16×32-bit general-purpose registers and two 72-bit accumulators optimized for DSP workloads.
Its clock system combines external crystal (8–24 MHz) and internal PLL with selectable HOCO (16/18/20 MHz) and LOCO (240 kHz) sources. Peripheral clocks are independently configurable: ICLK up to 120 MHz, PCLKA up to 120 MHz (for ETHERC, GLCDC, DRW2D), PCLKB up to 60 MHz (for TMR, CMT, S12AD unit 0), and PCLKD up to 60 MHz (for S12AD unit 1).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC core with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); enables real-time deterministic control in motor drives and protocol stacks |
| Flash Memory | 2 MB code flash with dual-bank structure - allows background programming and zero-downtime firmware updates |
| SRAM | 640 KB total: 256 KB main RAM + 384 KB expansion RAM, all accessible at 120 MHz with no wait states |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), 2-channel 12-bit D/A, on-chip temperature sensor (±1°C) |
| Connectivity | Ethernet MAC + PHY, 2× CAN (ISO11898-1), 3× RSPI, 1× QSPI, 3× I²C (up to 1 Mbps), 13× SCI, SDHI/SDSI/MMCIF |
| Security & Safety | AES-128/192/256, TSIP, MPU, Trusted Memory (TM), CRC calculator (8/32-bit), IWDT with window function, register write protection |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 × 24 mm, 0.5 mm pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital domains: AVCC0 powers ADC unit 0 and analog peripherals; AVCC1 powers ADC unit 1 and DAC; VCC supplies digital logic |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise timing; required for Ethernet MAC synchronization and RTC accuracy |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MDIO/MDC bus for configuring external or integrated PHY registers |
| ETH_TXD0–3 / ETH_RXD0–3 | Ethernet data lanes | 4-bit transmit/receive data paths for MII mode; RMII uses subset (TXD0/1, RXD0/1, TX_EN, CRS_DV) |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 Full-Speed interface | Integrated transceiver supports host/function/OTG; VBUS sensing enables automatic role detection |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); compatible with SD memory and SDIO cards per Physical Layer Spec v3.01 |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed - critical for unattended industrial gateways |
| Integrated Ethernet PHY | Eliminates need for external PHY IC; reduces BOM count and PCB area while maintaining IEEE 802.3u compliance (10/100 Mbps, MII/RMII) |
| Graphic-LCD controller (GLCDC) | Direct drive of monochrome/color LCD panels up to 1024×768; supports 3-layer superposition (background + 2 graphics planes) |
| 2D drawing engine (DRW2D) | Hardware-accelerated vector rendering (lines, circles, triangles) and bit blitting (copy, stretch, rotate) - offloads GUI tasks from CPU |
| IEC60730 Class B support | Built-in self-test functions: oscillation-stop detection, CRC calculation, IWDT windowing, A/D self-diagnostic, register write protection |
| Secure boot via Trusted Memory (TM) | Code flash region protected against read-out; only CPU instruction fetch allowed - prevents firmware reverse engineering and cloning |
Applications
| Industrial HMI Terminal | Smart Energy Gateway |
|---|---|
Use Scenario: Touch-enabled panel with local display, serial fieldbus connectivity, and remote cloud upload via Ethernet. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving GLCDC+DRW2D for UI rendering, managing SDHI for logging, and running TLS stack on FPU. Use Value: Integrated 2 MB flash stores full UI assets and firmware; dual CAN handles Modbus TCP bridging; Ethernet PHY enables direct LAN connection without external components. |
Use Scenario: DIN-rail mounted meter concentrator aggregating data from smart meters (via RS485/Modbus) and transmitting to utility SCADA over Ethernet. IC Role / Device Role / Timing Role: Real-time protocol gateway with deterministic timer-triggered A/D sampling, CAN/SCI protocol translation, and encrypted data forwarding. Use Value: Hardware AES ensures secure TLS handshake; dual-bank flash permits OTA updates during maintenance windows; 120 MHz CPU sustains concurrent Ethernet + CAN + SDIO traffic. |
| Secure Edge Node Controller | Networked Motor Drive Interface |
Use Scenario: Field-deployable PLC module with secure firmware update, tamper-resistant logging, and multi-protocol fieldbus support. IC Role / Device Role / Timing Role: Safety-certified controller executing IEC60730 diagnostics, managing encrypted data flash writes, and validating peripheral integrity via CRC and IWDT. Use Value: TSIP and Trusted Memory prevent unauthorized firmware access; on-chip temperature sensor monitors thermal derating; MPU isolates safety-critical tasks from application code. |
Use Scenario: Inverter control board requiring PWM generation, current sensing, encoder feedback, and EtherCAT or CANopen master functionality. IC Role / Device Role / Timing Role: Real-time motion controller using MTU3a for complementary PWM output with dead-time insertion, TPUa for encoder counting, and S12AD for current loop sampling. Use Value: 120 MHz CPU delivers sub-1 µs interrupt latency; hardware PWM timers ensure <10 ns jitter; integrated Ethernet supports firmware download and diagnostic streaming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDGLC#20 | Same RX65N Group silicon; differs only in code flash capacity (1.5 MB vs. 2 MB) and SRAM allocation (256 KB + 384 KB expansion vs. identical) | Lower flash density suits cost-sensitive designs where bootloader + application fit in ≤1.5 MB; same pinout and peripheral set | Select when firmware size is confirmed ≤1.5 MB and dual-bank update remains sufficient - avoids over-spec'ing flash |
| R5F566NEDGLC#20 | RX66N Group successor: higher CPU frequency (160 MHz), enhanced FPU, larger SRAM (1 MB), additional CAN FD channel, but different pinout and power sequencing | Targeted at next-gen applications requiring higher throughput (e.g., multi-axis servo control, AI inference at edge), not drop-in replacement | Choose for new designs needing >120 MHz performance or CAN FD; requires PCB redesign and software migration due to architectural differences |
Compared with R5F565NCDGLC#20, the R5F565NEDGLC#20 offers identical functionality at reduced flash capacity - ideal for cost-optimized deployments - while the R5F566NEDGLC#20 introduces architectural enhancements (160 MHz, CAN FD) that necessitate full hardware and software requalification.
Availability
R5F565NCDGLC#20 is available at Aetrix Electronics and suitable for industrial HMI, smart energy gateways, secure edge controllers, and networked motor drive interfaces requiring stable component supply across extended product lifecycles.
Supply support for R5F565NCDGLC#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX65N Group - including R5F565NCDGLC#20 - was engineered for high-integrity industrial applications demanding real-time performance, functional safety (IEC60730), and rich connectivity, with emphasis on HMI, gateway, and secure edge processing.
FAQ
What is the package type and pin count of the R5F565NCDGLC#20?
The R5F565NCDGLC#20 uses the PLQP0176KB-A package: a 176-pin LFBGA with 24 × 24 mm footprint and 0.5 mm pitch. This matches the maximum I/O configuration of the RX65N Group, supporting 136 general-purpose I/O pins with 5-V tolerance on 19 pins, open-drain capability, and programmable pull-up resistors - essential for industrial interfacing and noise immunity.
Does the R5F565NCDGLC#20 include an integrated Ethernet PHY?
Yes, the R5F565NCDGLC#20 integrates a full IEEE 802.3-compliant Ethernet PHY supporting both MII and RMII interfaces. It operates at 10/100 Mbps in full- and half-duplex modes, includes Magic Packet™ wake-on-LAN detection, and complies with IEEE 802.3x flow control - eliminating the need for an external PHY IC in most industrial Ethernet designs.
How does the dual-bank flash architecture benefit firmware updates on the R5F565NCDGLC#20?
The R5F565NCDGLC#20's dual-bank flash enables true background programming: one bank runs active firmware while the other is erased and reprogrammed. This allows zero-downtime field updates, critical for unattended industrial gateways and remote edge nodes. The start-up bank can be swapped atomically after validation, ensuring fail-safe recovery.
What safety certifications or built-in features support IEC60730 compliance for the R5F565NCDGLC#20?
The R5F565NCDGLC#20 includes multiple IEC60730 Class B–ready features: oscillation-stop detection, hardware CRC calculator (8/32-bit), independent watchdog timer (IWDT) with configurable window, self-diagnostic A/D converter test, register write protection, and memory protection unit (MPU). These are documented in Renesas Application Note R01AN3819JJ0100.
Can the R5F565NCDGLC#20 support simultaneous operation of Ethernet, CAN, and SD card interfaces?
Yes, the R5F565NCDGLC#20 is designed for concurrent high-bandwidth peripheral operation: Ethernet MAC (with dedicated EDMAC), dual CAN channels (32 mailboxes each), and SD host interface (SDHI) all operate independently with separate DMA channels (DMACAa, EXDMAC, DTCb) and clock domains (ICLK, PCLKA, PCLKB), enabling real-time data aggregation and forwarding without CPU bottlenecks.
R5F565NCDGLC#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 177-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NCDGLC#20 FAQ
1.How can I place an order for R5F565NCDGLC#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NCDGLC#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NCDGLC#20 reliable?
The price and inventory of R5F565NCDGLC#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NCDGLC#20 is usually 5 days.
3.What payment methods are accepted for R5F565NCDGLC#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NCDGLC#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NCDGLC#20?
R5F565NCDGLC#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NCDGLC#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NCDGLC#20?
For technical support, including R5F565NCDGLC#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NCDGLC#20 requirements.
6.How does Aetrix verify that R5F565NCDGLC#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NCDGLC#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NCDGLC#20 meets industry standards.
7.What is the process for return or replacement of R5F565NCDGLC#20?
All R5F565NCDGLC#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NCDGLC#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NCDGLC#20 part is unused and in its original packaging.
Return procedure for R5F565NCDGLC#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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