My Inquiry
My Account
Renesas R5F565NCDGLJ#20
- Part No.:
- R5F565NCDGLJ#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F565NCDGLJ#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 100TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F565NCDGLJ#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with on-chip FPU, 240 DMIPS performance, 2-MB code flash (dual-bank), 640-KB SRAM, Ethernet MAC, CAN, SD host/slave, QSPI, and hardware AES/TSIP encryption - deployed in industrial HMI, networked gateway, and secure IoT edge controllers.
For engineers reviewing the R5F565NCDGLJ#20 datasheet, R5F565NCDGLJ#20 pinout, R5F565NCDGLJ#20 application, or R5F565NCDGLJ#20 equivalent, key selection criteria include its 176-pin LFBGA package, -40°C to +105°C operating range, integrated GLCDC+DRW2D for embedded graphics, dual-bank flash for safe firmware updates, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565NCDGLJ#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code; it integrates a single-precision IEEE-754 FPU and two MAC units for deterministic DSP workloads. Clocking supports external crystal (8–24 MHz) or internal PLL with independent PCLKA (up to 120 MHz), PCLKB (up to 60 MHz), and dedicated ADCLK domains.
Its peripheral subsystem includes an Ethernet MAC with RMII/MII, dual CAN channels (32 mailboxes each), 13 SCI channels (including FIFO-equipped SCIi), 3 RSPI, 1 QSPI, SDHI/SDSI/MMCIF, GLCDC with 3-plane overlay, DRW2D vector/bitblit engine, and dual 12-bit A/D converters (8+21 channels) with self-diagnostic and disconnection detection - all coordinated via the Event Link Controller (ELC) for CPU-offload operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 Mbytes code flash with dual-bank structure enabling background programming and safe firmware swap |
| SRAM | 640 Kbytes main SRAM (no wait states @ 120 MHz) + 8 Kbytes battery-backed standby RAM |
| Operating Temp | -40°C to +105°C (G-version), qualified for extended industrial environments |
| Package | PLQP0176KB-A: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, 136 general-purpose I/Os (5-V tolerant on 19 pins) |
| Security | AES-128/192/256 + Trusted Secure IP (TSIP) for key management and encrypted boot |
| Real-time Clock | Dedicated RTC with leap-year correction, time-capture, and VBATT backup support |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5-mm ball pitch, RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital/analog supplies enable noise isolation; AVCC1 powers A/D and D/A converters |
| VBATT | Battery backup input | Supplies RTC during main power loss; supports long-term timekeeping without system reset |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system clock generation and USB timing compliance |
| MD0 / MD1 | Mode setting pins | Configure boot mode (SCI/USB/FINE) and memory mapping at reset release |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO bus for PHY configuration and status monitoring |
| RMII_RX0 / RMII_RX1 / RMII_CRS_DV / RMII_TXEN / RMII_TX0 / RMII_TX1 | Reduced Media Independent Interface | 6-pin RMII interface enables 10/100 Mbps Ethernet with minimal pin count and external PHY integration |
| CAN0_TX / CAN0_RX / CAN1_TX / CAN1_RX | CAN transceiver I/O | Dual ISO 11898-1 compliant CAN channels with 32 mailboxes each for automotive and industrial networking |
| QSPI_IO0–IO3 / QSPI_CLK / QSPI_CS | Quad SPI interface | Direct connection to quad-output serial flash for fast XIP execution and secure firmware storage |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s) for local data logging and firmware update storage |
| GLCDC_DOTCLK / GLCDC_DE / GLCDC_HSYNC / GLCDC_VSYNC / GLCDC_DATA0–23 | Graphic LCD controller outputs | 24-bit parallel RGB interface with programmable timing for direct drive of TFT panels up to WVGA |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Secure IP (TSIP) | Hardware-accelerated AES, SHA, RNG, and key wrapping with tamper-resistant key storage for secure boot and OTA updates |
| GLCDC + DRW2D | Integrated graphic-LCD controller with 3-plane overlay and 2D drawing engine supporting vector primitives, bitblit, rotation, and texture mapping - eliminates external GPU in HMI designs |
| Dual-bank Flash | Enables seamless firmware updates: new image programmed into inactive bank while active bank executes; bank swap on next reset ensures zero-downtime field upgrades |
| IEC60730 Safety Support | On-chip CRC calculator (CRCA), oscillation-stop detection, IWDT with window function, A/D self-test, and register write protection meet Class B requirements without external components |
| Event Link Controller (ELC) | 83 internal event sources routed without CPU intervention - e.g., TPU timer overflow triggers A/D conversion, SCI receive triggers DMA transfer, reducing latency and ISR overhead |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Standalone touch-enabled operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Primary application MCU executing real-time UI rendering via GLCDC+DRW2D, managing SD card logs, and handling CAN/Ethernet communication with control networks. Use Value: Integrated graphics engine eliminates external display controller; dual-bank flash enables silent firmware updates during machine runtime; TSIP secures remote access credentials and firmware images. | Use Scenario: Field-deployed protocol translator connecting legacy Modbus RTU devices to cloud platforms via TLS-secured MQTT over Ethernet. IC Role / Device Role / Timing Role: Central protocol stack processor with hardware crypto acceleration, dual CAN/Ethernet interfaces, and SDHI for offline cache and configuration backup. Use Value: AES/TSIP offloads TLS handshake and payload encryption; RMII Ethernet and dual CAN allow concurrent upstream/downstream traffic; 640-KB SRAM buffers large JSON payloads and protocol translation state. |
| Networked Energy Meter | Medical Device Controller |
Use Scenario: DIN-rail mounted smart meter with pulse counting, harmonic analysis, and secure DLMS/COSEM over TCP/IP. IC Role / Device Role / Timing Role: High-precision measurement controller running A/D sampling at 100 kSPS, performing FFT in FPU, and transmitting encrypted metering data via Ethernet. Use Value: Dual 12-bit A/D units (8+21 channels) support simultaneous voltage/current/harmonic capture; FPU accelerates real-time FFT; IEC60730 features satisfy medical-grade functional safety requirements. | Use Scenario: Portable diagnostic device with color LCD display, SD-based patient record storage, and USB host for peripheral attachment (e.g., thermal printer). IC Role / Device Role / Timing Role: System-on-chip managing touchscreen UI, GLCDC-driven display, SDHI for DICOM file storage, and USB 2.0 FS host for certified peripherals. Use Value: 240 DMIPS CPU handles real-time UI responsiveness; 2-MB flash stores full GUI assets and firmware; USBb module supports bus-powered printers without external hub logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDGLJ#20 | Same RX65N Group silicon; differs only in code flash capacity (1.5 MB vs. 2 MB) and SRAM (256 KB + 384 KB expansion vs. 640 KB unified) | Suitable where firmware footprint < 1.5 MB and graphics buffer requirements are lower | Select when cost optimization is prioritized and full 2-MB flash headroom is unnecessary |
| R5F566NEDGLJ#20 | Higher-performance RX66N variant: 160 MHz CPU, 320 DMIPS, enhanced TSIP (SHA-256, RSA), larger SRAM (1 MB), but no GLCDC/DRW2D | Better for compute-intensive cryptography or signal processing; lacks integrated graphics | Choose for security-critical gateways needing stronger crypto or higher throughput, not display-centric designs |
Compared with R5F565NEDGLJ#20, the R5F565NCDGLJ#20 provides guaranteed 2-MB flash and unified 640-KB SRAM for complex GUIs and field-upgradable firmware; versus R5F566NEDGLJ#20, it trades raw CPU speed and advanced crypto for integrated display control - making it optimal for cost-sensitive, graphics-heavy industrial edge nodes.
Availability
R5F565NCDGLJ#20 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and networked energy meters requiring stable component supply across multi-year production cycles.
Supply support for R5F565NCDGLJ#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets.
The RX65N Group targets high-integration industrial and networked applications requiring graphics, connectivity, security, and functional safety - with the R5F565NCDGLJ#20 optimized for display-rich, field-upgradable, and IEC60730-certifiable designs.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565NCDGLJ#20?
The R5F565NCDGLJ#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions. It delivers 240 DMIPS and includes a single-precision IEEE-754 floating-point unit, two MAC units, and a 32-bit multiplier with one-cycle execution - enabling deterministic real-time control and signal processing in the R5F565NCDGLJ#20.
Does the R5F565NCDGLJ#20 support secure firmware updates and cryptographic operations?
Yes, the R5F565NCDGLJ#20 integrates AES-128/192/256 and Trusted Secure IP (TSIP) for hardware-accelerated encryption, key management, and secure boot. Its dual-bank flash allows background programming of new firmware while the current version runs, followed by atomic bank swap - ensuring zero-downtime updates. These capabilities are fully implemented in the R5F565NCDGLJ#20 silicon and documented in Renesas Application Note R01AN3917.
What display interfaces and graphics capabilities does the R5F565NCDGLJ#20 provide?
The R5F565NCDGLJ#20 includes a Graphic-LCD Controller (GLCDC) supporting 24-bit RGB output with programmable timing, 3-plane overlay (background, graphic 1, graphic 2), and CLUT formats. It also integrates a 2D Drawing Engine (DRW2D) for vector drawing, bitblit, rotation, and texture mapping - eliminating need for external GPU in HMI designs. This full graphics subsystem is native to the R5F565NCDGLJ#20 and validated per Renesas Hardware Manual R01UH0579.
How many communication interfaces does the R5F565NCDGLJ#20 support, and which are hardware-accelerated?
The R5F565NCDGLJ#20 supports Ethernet MAC (10/100 Mbps RMII/MII), dual CAN 2.0B (32 mailboxes/channel), 13 SCI channels (including FIFO-equipped SCIi), 3 RSPI, 1 QSPI, SDHI/SDSI/MMCIF, USB 2.0 FS host/function, and I2C (3 channels, 1 Mbps). All are hardware-peripheral blocks with dedicated DMA channels (EDMAC, DMACAa, EXDMAC) - offloading CPU for sustained throughput in the R5F565NCDGLJ#20's industrial networking stack.
Is the R5F565NCDGLJ#20 qualified for extended temperature and safety-critical applications?
Yes, the R5F565NCDGLJ#20 is rated for -40°C to +105°C (G-version) and includes IEC60730 Class B support features: oscillation-stop detection, CRC calculator (CRCA), independent watchdog timer (IWDT) with window function, A/D converter self-diagnostic, and register write protection. These are silicon-verified functions in the R5F565NCDGLJ#20 and covered in Renesas Functional Safety Manual R01UH0580.
R5F565NCDGLJ#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NCDGLJ#20 FAQ
1.How can I place an order for R5F565NCDGLJ#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NCDGLJ#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NCDGLJ#20 reliable?
The price and inventory of R5F565NCDGLJ#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NCDGLJ#20 is usually 5 days.
3.What payment methods are accepted for R5F565NCDGLJ#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NCDGLJ#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NCDGLJ#20?
R5F565NCDGLJ#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NCDGLJ#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NCDGLJ#20?
For technical support, including R5F565NCDGLJ#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NCDGLJ#20 requirements.
6.How does Aetrix verify that R5F565NCDGLJ#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NCDGLJ#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NCDGLJ#20 meets industry standards.
7.What is the process for return or replacement of R5F565NCDGLJ#20?
All R5F565NCDGLJ#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NCDGLJ#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NCDGLJ#20 part is unused and in its original packaging.
Return procedure for R5F565NCDGLJ#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F565NCDGLJ#20 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
