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Renesas R5F565NCDGLK#20
- Part No.:
- R5F565NCDGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F565NCDGLK#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F565NCDGLK#20 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, GLCDC, DRW2D, and TSIP encryption. It targets industrial HMI, networked gateways, and secure IoT edge nodes requiring real-time control, graphics, and connectivity.
For engineers reviewing the R5F565NCDGLK#20 datasheet, R5F565NCDGLK#20 pinout, R5F565NCDGLK#20 application, or R5F565NCDGLK#20 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), 120 MHz system clock synchronized to PCLKA, dual-bank flash for safe firmware updates, 2-channel 12-bit D/A, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565NCDGLK#20 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions-enabling ultra-compact code and fast interrupt response. Its memory subsystem includes 2 MB dual-bank flash (with background programming/erasing), 640 KB zero-wait-state SRAM, and 8 KB standby RAM backed by VBATT.
Peripherals are clocked across multiple domains: PCLKA (up to 120 MHz) drives ETHERC, EDMAC, AES, GLCDC, and DRW2D; PCLKB (up to 60 MHz) serves TPU, MTU3, SCI, and A/D units; PCLKC/PCLKD (60 MHz) feed S12AD unit 0 and unit 1 respectively. The ELC enables hardware-triggered event chaining without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Flash Memory | 2 MB dual-bank code flash; supports background programming and bank-swapping at runtime |
| SRAM | 640 KB on-chip SRAM with zero wait states at 120 MHz operation |
| Operating Voltage | 2.7–3.6 V supply; supports RTC battery backup via VBATT pin |
| Real-Time Clock | RTC with leap-year correction, time-capture, and 30-second adjustment; operates from sub-clock or main clock |
| Security | Trusted Secure IP (TSIP) with AES-128/192/256; memory protection unit (MPU) with 8 configurable regions |
| Connectivity | Ethernet MAC (10/100 Mbps MII/RMII), 2-channel CAN (ISO11898-1), SD host/slave, QSPI, 3× RIIC, 13× SCI |
| Graphics & Imaging | Graphic-LCD controller (GLCDC) supporting 3-plane overlay; 2D drawing engine (DRW2D) with vector/bit-blit acceleration |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 × 24 mm, 0.5-mm pitch, RoHS compliant. Thermal pad exposed on underside for enhanced heat dissipation in industrial environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital supplies enable noise isolation for ADC/DAC and high-speed logic |
| VBATT | Battery backup input | Supplies RTC during main power loss; supports long-term calendar retention without external circuitry |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator for precise system timing and Ethernet PHY synchronization |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and single-chip vs. extended mode at reset release |
| ETH_MDC / ETH_MDIO | PHY management interface | Enable IEEE 802.3-compliant MDIO/MDC communication with external Ethernet PHY |
| SD0_CMD / SD0_CLK / SD0_DATx | SD host interface signals | Direct 1-/4-bit SD bus interface supporting high-speed mode (25 MB/s) per SD 3.01 spec |
| QSPI_IO0–IO3 | Quad SPI data lines | Enable x4 read/write to serial flash; programmable clock phase/polarity for timing margin optimization |
| GLCD_D0–D23 | RGB parallel LCD data bus | 24-bit RGB interface driving TFT panels up to WXGA resolution with GLCDC hardware scaling |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Safety Support | Oscillation-stop detection, CRC calculator (CRCA), IWDT windowing, self-diagnostic A/D, and register write protection meet Class B requirements |
| Dual-Bank Flash Architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed, eliminating downtime |
| Event Link Controller (ELC) | Hardware interconnect for 83 internal events eliminates CPU polling overhead for timer-triggered ADC, PWM, or DMA transfers |
| Trusted Secure IP (TSIP) | On-die cryptographic accelerator supporting AES encryption/decryption and key wrapping with tamper-resistant key storage |
| Graphics Subsystem Integration | GLCDC + DRW2D co-processing offloads CPU from pixel composition, rotation, and bit-blit operations in HMI applications |
| Flexible Clock Domain Partitioning | Independent PCLKA/PCLKB/PCLKC/PCLKD domains allow optimal peripheral clocking-e.g., 120 MHz for Ethernet, 60 MHz for ADC-without over-clocking entire system |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local graphics rendering and remote diagnostics. IC Role / Device Role / Timing Role: Primary application processor managing GLCDC-driven TFT display, touch controller via I2C, and real-time control loop via MTU3 timers. Use Value: Integrated DRW2D accelerates UI animations; dual-bank flash allows field-upgradable firmware without halting machine operation. | Use Scenario: Protocol-bridging gateway aggregating Modbus RTU sensors and forwarding data via Ethernet to cloud SCADA systems. IC Role / Device Role / Timing Role: Central protocol translator with CAN/RS485 physical layers, Ethernet MAC, and TLS-capable crypto via TSIP. Use Value: On-chip AES and SHA accelerate TLS handshake; integrated Ethernet MAC + PHY interface reduces BOM cost versus discrete PHY solutions. |
| Networked Building Controller | Medical Data Logger |
Use Scenario: HVAC controller with BACnet/IP support, local web server, and SD card-based log storage. IC Role / Device Role / Timing Role: Real-time controller running FreeRTOS, serving HTTP pages via embedded TCP/IP stack, and managing SDHI/SDSI for redundant logging. Use Value: Dual SD interfaces enable simultaneous host (log upload) and slave (configuration download) operation; 640 KB SRAM buffers large HTTP payloads and TLS session state. | Use Scenario: Portable patient monitor recording ECG waveforms, temperature, and SpO₂ to encrypted SD card with timestamped audit trail. IC Role / Device Role / Timing Role: Safety-certified data acquisition node using S12AD with self-diagnostic, RTC for ISO-compliant timestamps, and TSIP for HIPAA-compliant data encryption. Use Value: IEC60730-compliant IWDT and CRC ensure deterministic fail-safe behavior; temperature sensor + A/D unit 1 provide calibrated on-die thermal monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFP#30 | Same RX65N Group, 144-pin LFQFP package (PLQP0144KA-B); 2 MB flash, 640 KB SRAM, but fewer GPIO (111 vs. 136) and no SD slave interface | Lacks SD slave and 25-pin reduction limits peripheral expansion in space-constrained designs | Select when footprint size or PCB assembly cost outweighs need for SD slave or full I/O count |
| R5F566NHDDFK#30 | RX66N Group successor: 160 MHz CPU, 4 MB flash, 1 MB SRAM, enhanced TSIP-Lite, but requires updated toolchain and lacks GLCDC/DRW2D | No integrated graphics engine; targets higher-performance control-only applications without display needs | Choose for compute-intensive tasks where graphics are unnecessary and future-proofing justifies migration effort |
Compared with R5F565NCDGLK#20, R5F565NEHDFP#30 offers identical core peripherals in a smaller package but sacrifices SD slave and I/O count, while R5F566NHDDFK#30 delivers higher clock speed and memory but removes graphics acceleration-making R5F565NCDGLK#20 optimal for display-integrated industrial edge devices requiring field-upgradable firmware and safety certification.
Availability
R5F565NCDGLK#20 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and networked building controllers requiring stable component supply, long lifecycle support, and automotive-grade reliability under extended temperature conditions.
Supply support for R5F565NCDGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX65N Group-including R5F565NCDGLK#20-is designed for high-integrity human-machine interfaces and networked industrial equipment, integrating graphics, connectivity, security, and functional safety features in a single chip.
FAQ
What is the maximum operating frequency and core architecture of the R5F565NCDGLK#20?
The R5F565NCDGLK#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. This core features a CISC Harvard architecture with a 5-stage pipeline, variable-length instructions, and support for single-precision IEEE-754 floating-point arithmetic. Its design delivers 240 DMIPS performance and includes hardware multiply-and-accumulate units. The R5F565NCDGLK#20 also integrates a memory protection unit (MPU) and JTAG/FINE debugging interfaces for robust development and deployment.
Does the R5F565NCDGLK#20 support dual-bank flash for firmware updates?
Yes, the R5F565NCDGLK#20 includes 2 MB of on-chip code flash memory organized in a dual-bank structure. This enables background programming and erasing, allowing one bank to execute application code while the other is being updated-ensuring zero-downtime firmware upgrades. The R5F565NCDGLK#20 supports bank-swapping at startup, making it ideal for mission-critical industrial systems requiring high availability and field-upgradability without service interruption.
What graphics and display capabilities does the R5F565NCDGLK#20 provide?
The R5F565NCDGLK#20 integrates a Graphic-LCD Controller (GLCDC) supporting 3-plane overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing and bit-blit operations. It supports 24-bit RGB parallel output up to WXGA resolution and multiple pixel formats (32/16/8 bpp). These features eliminate the need for external graphics processors in industrial HMIs, reducing BOM cost and board space-key advantages of the R5F565NCDGLK#20 in display-centric applications.
How does the R5F565NCDGLK#20 meet IEC60730 Class B safety requirements?
The R5F565NCDGLK#20 incorporates multiple hardware features certified for IEC60730 Class B compliance: oscillation-stop detection, CRC calculator (CRCA), independent watchdog timer (IWDT) with windowing function, self-diagnostic A/D converter, and register write protection. These mechanisms enable runtime integrity checks, fault detection, and fail-safe behavior without software overhead. The R5F565NCDGLK#20's safety features are documented in Renesas' official safety manual and are leveraged in certified industrial control designs.
What is the package type and pin count of the R5F565NCDGLK#20?
The R5F565NCDGLK#20 uses the PLQP0176KB-A package: a 176-pin Low-Profile Quad Flat Package (LFBGA) measuring 24 × 24 mm with 0.5-mm pitch. It provides 136 general-purpose I/O pins, including 19 with 5-V tolerance, and supports multiple low-power modes. This package is optimized for thermal performance and signal integrity in industrial environments-making the R5F565NCDGLK#20 suitable for dense, high-reliability PCB layouts requiring robust mechanical and electrical characteristics.
R5F565NCDGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NCDGLK#20 FAQ
1.How can I place an order for R5F565NCDGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NCDGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NCDGLK#20 reliable?
The price and inventory of R5F565NCDGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NCDGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F565NCDGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NCDGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NCDGLK#20?
R5F565NCDGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NCDGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NCDGLK#20?
For technical support, including R5F565NCDGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NCDGLK#20 requirements.
6.How does Aetrix verify that R5F565NCDGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NCDGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NCDGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F565NCDGLK#20?
All R5F565NCDGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NCDGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NCDGLK#20 part is unused and in its original packaging.
Return procedure for R5F565NCDGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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