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Renesas R5F565NCHGFP#30
- Part No.:
- R5F565NCHGFP#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F565NCHGFP#30.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 100LFQFP
- Quantity:
- Payment:
- Shipping:
Inventory:180
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Product details
Overview
R5F565NCHGFP#30 from Renesas is a 120-MHz 32-bit RXv2 microcontroller with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 MB on-chip code flash memory (dual-bank), 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, and GLCDC for industrial HMI and networked embedded systems.
For engineers reviewing the R5F565NCHGFP#30 datasheet, R5F565NCHGFP#30 pinout, R5F565NCHGFP#30 application, or R5F565NCHGFP#30 equivalent, key selection considerations include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C operating range (G-version), dual-bank flash for safe firmware updates, hardware AES/TSIP encryption, and real-time clock with battery backup support.
Technical Context
The R5F565NCHGFP#30 implements the RXv2 CPU core with 5-stage CISC Harvard pipeline, variable-length instructions, and MPU-based memory protection. It integrates dual-clock domain operation: ICLK up to 120 MHz for CPU and PCLKA-synchronized peripherals (ETHERC, GLCDC, DRW2D), and PCLKB up to 60 MHz for most other modules including S12AD units and TMR timers.
Its peripheral architecture includes dedicated DMA controllers-DMACAa (8 channels), EXDMAC (2 channels), DTCb (1 channel)-and event linking via ELC to eliminate CPU intervention for timer-triggered ADC conversions, PWM dead-time compensation, or GPIO state changes. The device supports IEC60730 safety compliance through oscillation-stop detection, CRC calculation (CRCA), IWDT windowing, and register write protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS, IEEE-754 single-precision FPU |
| Memory | 2 MB code flash (dual-bank, BGO programming), 640 KB SRAM (no wait states), 32 KB data flash (100k erase cycles) |
| Operating Range | -40°C to +105°C (G-version), 2.7–3.6 V supply, 0.19 mA/MHz typical active current |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), CAN (2 channels, 32 mailboxes each), USB 2.0 FS host/function/OTG, SDHI/SDSI/MMCIF |
| Analog Peripherals | Two 12-bit A/D converters (8 + 21 channels), two 12-bit D/A converters, on-chip temperature sensor (±1°C) |
| Security & Safety | AES-128/192/256, TSIP, MPU (8 regions), CRCA, IWDT with window function, register write protection |
| Graphics & Timing | GLCDC (3-plane overlay), DRW2D (vector/bit-blit), RTC with battery backup, 25+ timers including MTU3a (9-channel) and TPUa (6-channel) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Quad Flat Package (LFBGA), 24 × 24 mm, 0.5-mm pitch, RoHS-compliant, G-version (-40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core (VCC), analog unit 0 (AVCC0), analog unit 1 (AVCC1); all require 2.7–3.6 V with local decoupling |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin cell or supercapacitor |
| RES# | Active-low reset input | Hardware reset assertion; internal POR/LVD also generates reset when VCC drops below threshold |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; enables high-accuracy clock source for Ethernet and USB timing |
| MD0–MD2 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and single-chip vs extended mode at power-on reset |
| ETXD0–7, ETX_EN, ETX_CLK, ERXD0–7, ERX_DV, ERX_CLK | Ethernet PHY interface | MII interface signals; RMII mode uses subset (ETXD0–1, ETX_EN, ERXD0–1, ERX_DV, ERX_CLK) |
| TXD0–3, RXD0–3, SCK0–2, SSL0–2, MOSI/MISO | SCI/RSPI/QSPI I/O | Configurable multi-protocol serial interfaces; SCIg/h/i support UART/SPI/I²C emulation; RSPIc offers 128-bit buffers |
| AD00–AD28 | Analog input channels | 29 total A/D inputs across two units; AD00–AD07 (unit 0), AD08–AD28 (unit 1); support sample-and-hold and disconnection detection |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables background programming while executing from alternate bank-critical for fail-safe OTA firmware updates |
| Hardware-accelerated cryptography | Integrated AES engine and Trusted Secure IP (TSIP) provide secure boot, key management, and encrypted communication without CPU overhead |
| Event Link Controller (ELC) | 83 internal event sources routed without CPU intervention-e.g., MTU3 PWM edge triggers ADC conversion or toggles GPIO |
| Graphics subsystem | GLCDC + DRW2D enables standalone GUI rendering: 3-layer composition, vector drawing, bit-blit with rotation/stretch, and CLUT support |
| IEC60730 Class B support | Oscillation-stop detection, CRC calculator (CRCA), IWDT windowing, self-diagnostic A/D, and register write protection meet functional safety requirements |
Applications
| Industrial HMI Panel | Networked PLC Controller |
|---|---|
Use Scenario: Standalone touch-enabled operator interface with local graphics rendering and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Primary MCU managing GLCDC display output, DRW2D graphics acceleration, capacitive touch via ADC, and Ethernet TCP/IP stack. Use Value: Eliminates external GPU and Ethernet PHY; dual-bank flash allows seamless firmware updates during runtime without display interruption. |
Use Scenario: Compact programmable logic controller with real-time I/O control, fieldbus connectivity, and web-based configuration. IC Role / Device Role / Timing Role: Central controller executing ladder logic, sampling analog sensors via S12AD, driving PWM outputs via MTU3, and communicating via CAN/Ethernet. Use Value: Integrated CAN (2 channels, 32 mailboxes) and Ethernet MAC reduce BOM cost; 120 MHz CPU ensures deterministic scan cycle times under load. |
| Secure Gateway Device | Smart Energy Meter |
Use Scenario: Edge gateway aggregating Zigbee/Z-Wave subnets and forwarding data to cloud via TLS-secured Ethernet or USB host. IC Role / Device Role / Timing Role: Security-first host processor running TLS stack, validating firmware signatures using TSIP, and managing secure USB mass storage or SD card logging. Use Value: Hardware AES and TSIP prevent key extraction; 32 KB data flash stores cryptographic keys and logs with 100k-cycle endurance. |
Use Scenario: Revenue-grade meter with metrology ADC interface, tamper detection, time-of-use billing, and HAN communication. IC Role / Device Role / Timing Role: Metrology co-processor interfacing to external ΔΣ ADC, maintaining accurate RTC with VBATT backup, and logging events to data flash. Use Value: On-chip RTC with leap-year adjustment and time-capture on external pulse ensures precise tariff switching; temperature sensor monitors die temp for ADC calibration compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHGFP#30 | Same RX65N Group, identical 176-pin LFBGA package, but rated for -40°C to +85°C (D-version) and features 1.5 MB flash instead of 2 MB | Suitable for commercial/industrial environments without extended temperature requirement; lacks dual-bank capability for full 2 MB firmware swap | Select R5F565NEHGFP#30 only if thermal margin permits and 1.5 MB flash suffices; verify bootloader compatibility with reduced bank size |
| R5F566NHGFP#30 | RX66N Group successor: higher 160 MHz CPU, 4 MB flash, enhanced TSIP-Lite, but different pinout (176-pin TFLGA, not LFBGA) and no SD slave interface | Targets next-gen designs requiring higher performance and larger code space; incompatible with existing R5F565NCHGFP#30 PCB layout | R5F566NHGFP#30 is not a drop-in replacement; requires new layout and driver adaptation due to changed peripheral mapping and package type |
Compared with R5F565NEHGFP#30, the R5F565NCHGFP#30 provides extended temperature operation and full 2 MB dual-bank flash for robust field updates; versus R5F566NHGFP#30, it retains SD slave and exact pin compatibility but trades peak performance for proven maturity and layout reuse.
Availability
R5F565NCHGFP#30 is available at Aetrix Electronics and suitable for industrial HMI panels, networked PLC controllers, secure gateways, and smart energy meters requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability validation.
Supply support for R5F565NCHGFP#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The R5F565NCHGFP#30 belongs to the RX65N Group-a high-integration 32-bit MCU family designed for industrial human-machine interfaces, networked control systems, and safety-certifiable embedded devices requiring graphics, connectivity, and security.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565NCHGFP#30?
The R5F565NCHGFP#30 operates at a maximum frequency of 120 MHz using the RXv2 32-bit CISC Harvard CPU core with 5-stage pipeline, variable-length instructions, and single-precision IEEE-754 floating-point unit. It delivers 240 DMIPS performance and supports memory protection via an 8-region MPU. This architecture enables deterministic real-time execution in industrial control applications where the R5F565NCHGFP#30 serves as the primary system controller.
Does the R5F565NCHGFP#30 support dual-bank flash for firmware updates?
Yes, the R5F565NCHGFP#30 includes a dual-bank flash structure within its 2 MB code flash memory, enabling background programming (BGO) of one bank while executing code from the other. This allows safe over-the-air (OTA) firmware updates without system interruption-critical for unattended industrial equipment. The R5F565NCHGFP#30's bootloader must be configured to manage bank swapping and startup address redirection, and both banks support independent erase/program operations.
What graphics and display capabilities does the R5F565NCHGFP#30 provide?
The R5F565NCHGFP#30 integrates a Graphic-LCD Controller (GLCDC) supporting 3-plane overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) for vector drawing, bit-blit, rotation, and stretching. It handles 32-/16-/8-bit pixel formats and CLUT-based color lookup. These peripherals allow the R5F565NCHGFP#30 to drive QVGA–XGA displays directly without external GPU, making it ideal for cost-sensitive industrial HMI designs where the R5F565NCHGFP#30 manages both UI logic and rendering.
Which communication interfaces are integrated into the R5F565NCHGFP#30?
The R5F565NCHGFP#30 integrates Ethernet MAC (10/100 Mbps, MII/RMII), two CAN 2.0B channels (32 mailboxes each), USB 2.0 Full-Speed host/function/OTG, SD host/slave interfaces, three RSPI channels, quad SPI, three I²C buses (up to 1 Mbps), and up to 13 SCI channels supporting UART/SPI/I²C emulation. This comprehensive set enables the R5F565NCHGFP#30 to serve as a central hub in multi-protocol industrial networks-connecting to HMIs, sensors, actuators, and cloud gateways without external transceivers or bridge ICs.
How does the R5F565NCHGFP#30 support functional safety standards like IEC60730?
The R5F565NCHGFP#30 includes multiple hardware features for IEC60730 Class B compliance: oscillation-stop detection, CRC calculator (CRCA) with configurable polynomials, independent watchdog timer (IWDT) with windowing, self-diagnostic A/D converter, and register write protection. These functions allow runtime verification of clock integrity, memory consistency, and peripheral health-enabling the R5F565NCHGFP#30 to meet safety requirements in appliances, motor drives, and industrial controls where certified failure detection is mandatory.
R5F565NCHGFP#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NCHGFP#30 FAQ
1.How can I place an order for R5F565NCHGFP#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NCHGFP#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NCHGFP#30 reliable?
The price and inventory of R5F565NCHGFP#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NCHGFP#30 is usually 5 days.
3.What payment methods are accepted for R5F565NCHGFP#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NCHGFP#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NCHGFP#30?
R5F565NCHGFP#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NCHGFP#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NCHGFP#30?
For technical support, including R5F565NCHGFP#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NCHGFP#30 requirements.
6.How does Aetrix verify that R5F565NCHGFP#30 is sourced from the original manufacturer or authorized distributors?
All R5F565NCHGFP#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NCHGFP#30 meets industry standards.
7.What is the process for return or replacement of R5F565NCHGFP#30?
All R5F565NCHGFP#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NCHGFP#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NCHGFP#30 part is unused and in its original packaging.
Return procedure for R5F565NCHGFP#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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