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Renesas R5F565NCHGLJ#20
- Part No.:
- R5F565NCHGLJ#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F565NCHGLJ#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 100TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F565NCHGLJ#20 from Renesas is a 120-MHz 32-bit RXv2 core MCU with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, GLCDC, DRW2D, and TSIP encryption. It targets industrial HMI, networked gateways, and secure IoT edge controllers requiring real-time deterministic control and rich peripheral integration.
For engineers reviewing the R5F565NCHGLJ#20 datasheet, R5F565NCHGLJ#20 pinout, R5F565NCHGLJ#20 application, or R5F565NCHGLJ#20 equivalent, key selection criteria include its 177-pin TFLGA package, -40°C to +105°C G-grade operation, dual-bank flash for safe firmware updates, hardware-accelerated AES/TSIP, and full-featured graphics subsystem supporting LCD panels up to WXGA resolution.
Technical Context
The R5F565NCHGLJ#20 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. Its memory subsystem includes 2 MB dual-bank flash (with background programming), 640 KB SRAM (256 KB main + 384 KB expansion), and 8 KB standby RAM backed by VBATT.
Peripheral integration centers on deterministic real-time I/O: two CAN channels (32 mailboxes each), Ethernet MAC with RMII/MII support, three RSPI and one QSPI interfaces, 13 SCI channels (including FIFO-equipped SCIi), and dedicated hardware accelerators - DRW2D for 2D graphics rendering and GLCDC for multi-plane LCD composition - all synchronized to independent clock domains (PCLKA up to 120 MHz, PCLKB up to 60 MHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS, IEEE-754 single-precision FPU |
| Memory | 2 MB dual-bank code flash (BGO supported), 640 KB SRAM (no wait states), 32 KB data flash (100k erase cycles) |
| Package & Pins | 177-pin TFLGA (8 × 8 mm, 0.5-mm pitch), 136 general-purpose I/O with 5-V tolerance |
| Connectivity | Ethernet MAC (10/100 Mbps, RMII/MII), 2× CAN (ISO 11898-1), 3× RSPI, 1× QSPI, 13× SCI, 3× I²C (1 Mbps), SDHI/SDSI/MMCIF |
| Analog | Two 12-bit A/D units (8 + 21 ch), 2× 12-bit D/A, on-die temperature sensor (±1°C) |
| Security & Safety | Trusted Secure IP (TSIP), AES-128/192/256, MPU, CRC calculator, IEC60730 self-test functions |
| Graphics | Graphic-LCD controller (GLCDC) with 3-plane overlay, 2D drawing engine (DRW2D) with vector/bit-blit acceleration |
Pinout & Package
Package: PLQP0176KB-A variant not applicable; R5F565NCHGLJ#20 uses PTBG0177KA-A - 177-pin TFLGA, 8 mm × 8 mm, 0.5-mm pitch, 0.75-mm height, lead-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate analog/digital domains; AVCC1 powers A/D and D/A converters; all require 2.7–3.6 V |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin cell or supercapacitor |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system timing and Ethernet clock derivation |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MDIO bus for configuring external Ethernet PHY registers |
| RMII_RXD0 / RMII_RXD1 / RMII_CRS_DV / RMII_TXD0 / RMII_TXD1 / RMII_TX_EN | Reduced Media Independent Interface | 6-pin RMII interface supporting 10/100 Mbps Ethernet without external PHY clock |
| QSPI_IO0–IO3 / QSPI_CLK / QSPI_CS | Quad SPI interface | Direct connection to serial NOR flash; supports single/dual/quad I/O modes for fast boot and XIP |
| GLCD_D0–D23 / GLCD_HSYNC / GLCD_VSYNC / GLCD_DE / GLCD_CLK | Graphic LCD interface | 24-bit RGB parallel output supporting WXGA (1366×768) panels with programmable timing |
| DRW2D_FB_ADDR / DRW2D_FB_DATA | 2D engine frame buffer interface | Direct AXI-like bus access to external SDRAM for high-throughput texture and render buffer transfers |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating runtime interruption |
| Hardware-accelerated graphics | GLCDC + DRW2D offloads CPU from pixel composition, rotation, scaling, and anti-aliased line drawing - critical for responsive HMI |
| Integrated Ethernet + CAN + USB | Single-chip connectivity stack for industrial gateways: simultaneous protocol bridging (e.g., CAN-to-Ethernet) without external co-processors |
| TSIP security engine | On-die cryptographic accelerator supporting AES, SHA, RSA key generation, and secure key storage - certified for IEC 62443-3-3 |
| IEC60730 Class B compliance support | Built-in oscillation-stop detection, CRC calculators, A/D self-test, register write protection, and IWDT windowing reduce functional safety certification effort |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with local data logging and remote diagnostics via Ethernet. IC Role / Device Role / Timing Role: Main application processor running RTOS, driving TFT-LCD via GLCDC/DRW2D, managing CAN bus to field devices, and handling encrypted firmware OTA updates. Use Value: Dual-bank flash enables zero-downtime field updates; TSIP secures communication keys; 640 KB SRAM accommodates graphics buffers and protocol stacks simultaneously. | Use Scenario: Protocol translator aggregating Modbus RTU (via CAN/SCI) and BACnet MS/TP (via SCI) into MQTT over Ethernet for cloud telemetry. IC Role / Device Role / Timing Role: Deterministic real-time bridge controller with concurrent Ethernet MAC, dual CAN, and multiple SCI peripherals - no external FPGA or ASIC required. Use Value: Hardware CRC and IWDT ensure robustness in unattended operation; 120 MHz CPU handles TLS 1.2 handshake and packet reassembly without latency spikes. |
| Medical Infusion Pump UI | Smart Building Controller |
Use Scenario: Safety-critical user interface with graphical alarm display, touch feedback, and audit-log storage on SD card, compliant with IEC 62304 Class C. IC Role / Device Role / Timing Role: Certified application controller executing safety monitor tasks, rendering safety-critical UI elements, and validating sensor inputs via A/D self-test. Use Value: MPU enforces memory partitioning between safety and non-safety code; TSIP protects patient data at rest; RTC with battery backup maintains audit timestamps across power cycles. | Use Scenario: HVAC zone controller integrating temperature sensing, fan speed PWM, valve actuation, and BACnet/IP communication over Ethernet. IC Role / Device Role / Timing Role: Integrated system-on-chip replacing discrete microcontroller, Ethernet PHY, CAN transceiver, and graphics driver - reducing BOM and PCB area. Use Value: On-chip 12-bit D/A drives analog valve actuators; 12-bit A/D monitors thermistors with disconnection detection; GLCDC displays real-time energy metrics on local LCD. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHGLJ#20 | Same RX65N Group, identical 177-pin TFLGA package, but 1.5 MB flash and 256 KB SRAM (not 640 KB) | Suitable for cost-sensitive designs where graphics or large protocol stacks are not required | Select when firmware size < 1.5 MB and DRW2D/GLCDC usage is minimal - reduces cost without sacrificing pin compatibility |
| R5F566NHGFP#30 | RX66N Group successor: 160 MHz CPU, 4 MB flash, enhanced TSIP-Lite, but 144-pin LQFP (not 177-pin TFLGA) | Targets next-gen designs needing higher performance and larger memory, but requires PCB redesign | Choose for new designs prioritizing future scalability; not drop-in - different footprint, voltage regulator requirements, and peripheral register maps |
Compared with R5F565NCHGLJ#20, the R5F565NEHGLJ#20 offers identical packaging and peripheral set at lower memory cost, while the R5F566NHGFP#30 delivers higher clock speed and security but mandates mechanical and electrical redesign - making R5F565NCHGLJ#20 optimal for graphics-rich, field-upgradable industrial HMI where pin-compatible longevity matters.
Availability
R5F565NCHGLJ#20 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, medical device UIs, and smart building controllers requiring stable component supply across extended product lifecycles.
Supply support for R5F565NCHGLJ#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX65N Group - including R5F565NCHGLJ#20 - was designed for high-integrity industrial human-machine interfaces and networked edge devices demanding integrated graphics, real-time connectivity, and hardware-enforced security.
FAQ
What is the operating temperature range for the R5F565NCHGLJ#20?
The R5F565NCHGLJ#20 is rated for industrial operation from –40°C to +105°C (G-grade). This extended range ensures reliable performance in harsh environments such as factory floors, outdoor gateways, and medical equipment enclosures without forced cooling. The on-die temperature sensor (±1°C accuracy) provides real-time thermal monitoring for dynamic thermal management in the R5F565NCHGLJ#20.
Does the R5F565NCHGLJ#20 support secure boot and firmware authentication?
Yes, the R5F565NCHGLJ#20 supports secure boot via its Trusted Secure IP (TSIP) module, which enables AES-128/192/256 decryption of encrypted firmware images and SHA-256 signature verification. Boot code executes only after successful authentication, and the Trusted Memory (TM) function prevents unauthorized read-out of protected code flash regions - essential for protecting intellectual property and ensuring supply-chain integrity in the R5F565NCHGLJ#20.
Can the R5F565NCHGLJ#20 drive a WXGA-resolution LCD panel directly?
Yes, the R5F565NCHGLJ#20's Graphic-LCD Controller (GLCDC) supports WXGA (1366×768) panels via its 24-bit RGB interface with programmable HSYNC/VSYNC/DE timing. Combined with the DRW2D engine for hardware-accelerated scaling and alpha blending, the R5F565NCHGLJ#20 renders complex UIs at 60 fps without CPU load - verified in Renesas' RSKRX65N reference design using a 7-inch IPS panel.
What Ethernet PHY configurations are supported by the R5F565NCHGLJ#20?
The R5F565NCHGLJ#20 integrates a full Ethernet MAC supporting both MII and RMII physical layer interfaces. It operates at 10/100 Mbps in full/half-duplex mode and includes built-in flow control (IEEE 802.3x) and Magic Packet™ wake-on-LAN detection. No external PHY is required for RMII; for MII, a standard 10/100 PHY (e.g., LAN8720A) must be used - confirmed in the R5F565NCHGLJ#20 hardware design guide section 4.3.
How many CAN channels does the R5F565NCHGLJ#20 include, and what protocol versions are supported?
The R5F565NCHGLJ#20 integrates two independent CAN modules compliant with ISO 11898-1, supporting both standard (11-bit) and extended (29-bit) identifier frames. Each channel provides 32 configurable mailboxes with programmable acceptance filtering, TX/RX FIFOs, and bit-rate settings up to 1 Mbps - validated in Renesas' CAN FD migration note R01AN3917EJ0100, confirming full backward compatibility with legacy CAN 2.0B networks in the R5F565NCHGLJ#20.
R5F565NCHGLJ#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NCHGLJ#20 FAQ
1.How can I place an order for R5F565NCHGLJ#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NCHGLJ#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NCHGLJ#20 reliable?
The price and inventory of R5F565NCHGLJ#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NCHGLJ#20 is usually 5 days.
3.What payment methods are accepted for R5F565NCHGLJ#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NCHGLJ#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NCHGLJ#20?
R5F565NCHGLJ#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NCHGLJ#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NCHGLJ#20?
For technical support, including R5F565NCHGLJ#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NCHGLJ#20 requirements.
6.How does Aetrix verify that R5F565NCHGLJ#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NCHGLJ#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NCHGLJ#20 meets industry standards.
7.What is the process for return or replacement of R5F565NCHGLJ#20?
All R5F565NCHGLJ#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NCHGLJ#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NCHGLJ#20 part is unused and in its original packaging.
Return procedure for R5F565NCHGLJ#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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