Renesas R5F565NEDGLJ#20
- Part No.:
- R5F565NEDGLJ#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F565NEDGLJ#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 100TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
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Product details
Overview
R5F565NEDGLJ#20 from Renesas is a 32-bit RXv2 microcontroller with 120 MHz CPU, 240 DMIPS performance, single-precision IEEE-754 FPU, 2 MB on-chip code flash, 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, and GLCDC for industrial HMI and networked embedded control.
For engineers reviewing the R5F565NEDGLJ#20 datasheet, R5F565NEDGLJ#20 pinout, R5F565NEDGLJ#20 application, or R5F565NEDGLJ#20 equivalent, key selection criteria include dual-bank flash for safe firmware updates, 136 GPIO with 5-V tolerance, 12-bit A/D (21-channel unit), TSIP-based AES-256 encryption, and -40°C to +105°C operation in PLQP0176KB-A package.
Technical Context
The R5F565NEDGLJ#20 implements the RXv2 CISC Harvard architecture with 5-stage pipeline, variable-length instructions, and MPU-enforced memory protection. It integrates dedicated clocks for subsystems: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/DRW2D/GLCDC, and PCLKB up to 60 MHz for timers and ADC.
Its peripheral coherency is managed via Event Link Controller (ELC) supporting 83 internal event signals, enabling timer-triggered ADC conversions, PWM dead-time compensation, and hardware-synchronized DMA transfers without CPU intervention - critical for deterministic real-time control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit, 120 MHz max, 240 DMIPS - enables real-time deterministic execution of complex control algorithms. |
| Memory | 2 MB code flash (dual-bank), 640 KB SRAM, 32 KB data flash - supports background programming and firmware rollback. |
| FPU | Single-precision IEEE-754 compliant - accelerates motor control math, sensor fusion, and floating-point signal processing. |
| Connectivity | Ethernet MAC (10/100 Mbps), 2× CAN, 3× RSPI, 1× QSPI, 3× I²C, 13× SCI - enables multi-protocol industrial networking. |
| Analog | Two 12-bit A/D units (8 + 21 channels), 2× 12-bit D/A, on-die temperature sensor (±1°C) - supports precision analog I/O for closed-loop systems. |
| Security | TSIP with AES-128/192/256, Trusted Memory (TM), CRC calculator, register write protection - meets IEC 60730 Class B requirements. |
| Package | PLQP0176KB-A, 176-pin LQFP, 24 × 24 mm, 0.5-mm pitch - provides 136 general-purpose I/O pins with 5-V tolerance. |
| Temp Range | -40°C to +105°C (G-version) - qualified for extended-temperature industrial and automotive under-hood applications. |
Pinout & Package
PLQP0176KB-A is a 176-pin LQFP package (24 × 24 mm, 0.5-mm pitch) with 136 general-purpose I/O pins, 19 of which are 5-V tolerant, plus dedicated power, clock, reset, debug (JTAG/FINE), and peripheral function pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital/analog domains enable noise isolation for high-precision ADC/DAC operation. |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal for precise system timing and Ethernet PHY synchronization. |
| RES# | Active-low reset input | Hardware reset assertion compatible with standard push-button or supervisor IC circuits. |
| MD0 / MD1 | Mode setting pins | Determine boot source (on-chip ROM, SCI, USB, FINE) at power-on reset - critical for field firmware recovery. |
| ETXD0–ETXD3 / ERXD0–ERXD3 | Ethernet MAC physical layer I/O | Direct MII/RMII interface to external PHY - eliminates need for glue logic in 10/100 Mbps designs. |
| TXD0 / RXD0 | SCI0 asynchronous serial interface | UART channel for debug console, configuration, or host communication - supports baud rates up to 15 Mbps. |
| PE0–PE15 | General-purpose I/O port E | Configurable as GPIO, MTU3 waveform outputs, or ELC-linked event sources - enables hardware-triggered state transitions. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates with zero downtime: one bank executes while the other is reprogrammed in background. |
| Event Link Controller (ELC) | Eliminates CPU polling by directly connecting 83 internal peripherals - e.g., TPU output triggers ADC conversion without ISR overhead. |
| Graphic-LCD controller (GLCDC) | Drives up to 1024 × 768 panels with 3-layer overlay (background + 2 graphics planes) - reduces external frame buffer memory requirement. |
| 2D drawing engine (DRW2D) | Accelerates vector rendering (lines, circles), bit blitting, and texture mapping - offloads GUI computation from main CPU core. |
| Trusted Secure IP (TSIP) | Hardware-accelerated AES-256 and secure key storage - protects firmware integrity and enables secure OTA updates. |
| IEC 60730-compliant safety functions | Includes oscillation-stop detection, CRC calculator, IWDT windowing, and A/D self-diagnostic - simplifies Class B certification effort. |
Applications
| Industrial HMI Panel | Smart Gateway Device |
|---|---|
Use Scenario: Touch-enabled factory operator interface with local graphics rendering and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving LCD via GLCDC/DRW2D, and managing dual-network (Ethernet + CAN) communication stack. Use Value: Integrated 2 MB flash stores full GUI assets and firmware; 640 KB SRAM accommodates multitasking OS and protocol buffers without external RAM. | Use Scenario: Protocol translator bridging Modbus RTU field devices to cloud via MQTT over Ethernet/Wi-Fi (via external PHY). IC Role / Device Role / Timing Role: Central protocol engine performing real-time packet parsing, encryption (AES-256), and time-stamped event logging using RTC and standby RAM. Use Value: Dual CAN + Ethernet + SDIO interfaces allow concurrent fieldbus and upstream connectivity; TSIP ensures secure firmware and data transmission. |
| Networked Motor Drive | Secure Edge Node |
Use Scenario: Compact servo drive with position feedback, current sensing, and EtherCAT or PROFINET slave capability. IC Role / Device Role / Timing Role: Real-time motion controller using MTU3 complementary PWM with dead-time insertion, synchronized ADC sampling, and Ethernet MAC for fieldbus interface. Use Value: Hardware-peripheral coherency (ELC) guarantees sub-microsecond jitter between PWM edge and ADC trigger - essential for current loop stability. | Use Scenario: Battery-powered environmental sensor node with encrypted data logging to SD card and wake-on-LAN triggered uploads. IC Role / Device Role / Timing Role: Low-power host managing sensor A/D, AES-encrypted storage, RTC alarm wakeup, and Ethernet link management in deep software standby mode. Use Value: 0.19 mA/MHz active power + deep software standby with 8 KB backup RAM enables multi-year battery life with periodic secure reporting. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHGLJ#20 | Same RX65N Group, identical 2 MB flash/SRAM/peripherals, but in PLQP0176KB-A package with different marking - functionally identical die. | No functional difference; used interchangeably in production where marking variant is acceptable. | Select when sourcing flexibility or alternate traceability is required without design change. |
| R5F566NEDFLJ#20 | RX66N Group successor: higher 160 MHz CPU, enhanced TSIP-Lite, additional CAN FD channel, but no GLCDC/DRW2D and reduced SDHI bandwidth. | Better for compute-intensive, security-critical gateway roles; unsuitable for display-centric HMI due to missing graphics IP. | Choose for future-proofing in non-display applications requiring CAN FD or higher crypto throughput - not drop-in compatible. |
Compared with R5F565NEDGLJ#20, R5F565NEHGLJ#20 offers identical functionality with alternate marking, while R5F566NEDFLJ#20 trades graphics acceleration for higher CPU speed and CAN FD - making the former a direct logistics alternative and the latter a next-generation upgrade path for non-HMI use cases.
Availability
R5F565NEDGLJ#20 is available at Aetrix Electronics and suitable for industrial HMI, smart gateways, networked motor drives, and secure edge nodes requiring stable component supply across long-lifecycle manufacturing programs.
Supply support for R5F565NEDGLJ#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and infrastructure markets.
The RX65N Group, including R5F565NEDGLJ#20, was designed for high-integration industrial applications demanding real-time performance, rich connectivity, graphics capability, and functional safety compliance - particularly HMI, gateway, and motor control systems.
FAQ
What is the maximum operating frequency and performance rating of the R5F565NEDGLJ#20?
The R5F565NEDGLJ#20 operates at a maximum frequency of 120 MHz and delivers 240 DMIPS performance. Its RXv2 CPU core includes single-cycle 32-bit multiply and two-cycle divide instructions, along with a single-precision IEEE-754 FPU - enabling efficient execution of control algorithms and signal processing tasks in the R5F565NEDGLJ#20.
Does the R5F565NEDGLJ#20 support dual-bank flash for safe firmware updates?
Yes, the R5F565NEDGLJ#20 features a dual-bank flash architecture allowing background programming and bank swapping. This enables live firmware updates without interrupting application execution - a critical capability for maintaining uptime in industrial systems using the R5F565NEDGLJ#20.
What graphics capabilities does the R5F565NEDGLJ#20 integrate?
The R5F565NEDGLJ#20 integrates a Graphic-LCD Controller (GLCDC) supporting up to 1024 × 768 resolution with three overlay planes, and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector rendering and bit blitting. These features eliminate the need for external graphics controllers in HMI applications built around the R5F565NEDGLJ#20.
Which communication interfaces are available on the R5F565NEDGLJ#20 for industrial networking?
The R5F565NEDGLJ#20 includes Ethernet MAC (10/100 Mbps MII/RMII), two CAN 2.0B channels (32 mailboxes each), three RSPI, one QSPI, three I²C, 13 SCI channels, SD host/slave, and MMCIF - providing comprehensive multi-protocol support for industrial gateways and control systems based on the R5F565NEDGLJ#20.
Is the R5F565NEDGLJ#20 qualified for extended temperature operation?
Yes, the R5F565NEDGLJ#20 is rated for -40°C to +105°C operation (G-version), making it suitable for harsh industrial environments and under-hood automotive applications. Its low-power design draws only 0.19 mA/MHz typical, supporting thermal efficiency in sealed enclosures using the R5F565NEDGLJ#20.
R5F565NEDGLJ#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NEDGLJ#20 FAQ
1.How can I place an order for R5F565NEDGLJ#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NEDGLJ#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NEDGLJ#20 reliable?
The price and inventory of R5F565NEDGLJ#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NEDGLJ#20 is usually 5 days.
3.What payment methods are accepted for R5F565NEDGLJ#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NEDGLJ#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NEDGLJ#20?
R5F565NEDGLJ#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NEDGLJ#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NEDGLJ#20?
For technical support, including R5F565NEDGLJ#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NEDGLJ#20 requirements.
6.How does Aetrix verify that R5F565NEDGLJ#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NEDGLJ#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NEDGLJ#20 meets industry standards.
7.What is the process for return or replacement of R5F565NEDGLJ#20?
All R5F565NEDGLJ#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NEDGLJ#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NEDGLJ#20 part is unused and in its original packaging.
Return procedure for R5F565NEDGLJ#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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