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Renesas R5F565NEHGBG#20
- Part No.:
- R5F565NEHGBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F565NEHGBG#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:288
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Product details
Overview
R5F565NEHGBG#20 from Renesas is a 120-MHz 32-bit RXv2 core MCU with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 MB on-chip code flash (dual-bank), 640 KB SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, GLCDC, DRW2D, and TSIP encryption. It targets industrial HMI, networked gateways, and secure edge controllers requiring real-time deterministic execution, graphics rendering, and protocol offload.
For engineers reviewing the R5F565NEHGBG#20 datasheet, R5F565NEHGBG#20 pinout, R5F565NEHGBG#20 application, or R5F565NEHGBG#20 equivalent, key selection criteria include its 176-pin LFBGA package (PLQP0176KB-A), -40°C to +105°C G-grade operation, 2-channel CAN with 32 mailboxes per channel, 12-bit dual A/D converters (8+21 channels), and hardware-accelerated AES/TSIP for IEC60730-compliant safety firmware.
Technical Context
The R5F565NEHGBG#20 implements the RXv2 CPU core with 5-stage CISC Harvard pipeline, variable-length instructions, and MPU-enforced memory protection. Its clock system integrates PLL, HOCO/LOCO oscillators, and independent PCLK domains-PCLKA up to 120 MHz for ETHERC/EDMAC/GLCDC/DRW2D, PCLKB up to 60 MHz for most peripherals including S12AD units, and dedicated ADCLK for A/D conversion.
It supports full IEC60730 Class B compliance via oscillation-stop detection, CRC calculation (CRCA), IWDT windowing, register write protection, and self-diagnostic A/D functions. The ELC enables zero-CPU-latency peripheral event chaining-e.g., MTU3 PWM trigger → S12AD conversion start → DMA transfer completion → interrupt-all without software intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard, 120 MHz max, 240 DMIPS, IEEE-754 FPU, 72-bit accumulators |
| Memory | 2 MB dual-bank code flash (no-wait ≤50 MHz), 640 KB SRAM (no-wait at 120 MHz), 32 KB data flash (100k erase cycles) |
| Peripherals | Ethernet MAC (10/100 Mbps MII/RMII), 2× CAN (ISO11898-1, 32 mailboxes/channel), SDHI/SDSI/MMCIF, QSPI, GLCDC + DRW2D |
| Analog | Two 12-bit S12AD units (8 + 21 channels, 0.48 µs/ch), 2× R12DA (buffered/unbuffered), on-die temperature sensor (±1°C) |
| Security & Safety | TSIP encryption engine (AES-128/192/256), CRCA, IWDT with window function, MPU (8 regions), register write protection |
| Package & Temp | PLQP0176KB-A 176-pin LFBGA (24 × 24 mm, 0.5 mm pitch), G-grade: –40°C to +105°C |
| I/O & Timing | 136 general-purpose I/O (5-V tolerant, open-drain, pull-up), 25 timers including MTU3a (9-channel), TPUa (6-channel), CMTW (32-bit) |
Pinout & Package
Package: PLQP0176KB-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm body, 0.5 mm ball pitch, 13 × 13 array (excluding corner balls), standard JEDEC MO-277 compliant footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core (VCC), analog unit 0 (AVCC0), analog unit 1 (AVCC1) - all require 2.7–3.6 V with local decoupling |
| VBATT | Battery backup supply | Provides RTC power during main supply loss; connects to coin cell or supercap for calendar retention |
| XTAL/EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal for precise system clock generation and RTC reference |
| ETH_MDC/MDIO | IEEE 802.3 management interface | Enables PHY register access and status monitoring over MDIO bus; requires 50 Ω termination |
| CAN0_TX/CAN0_RX | Channel 0 CAN transceiver I/O | Differential pair for ISO11898-1 compliant CAN bus; requires external 120 Ω termination resistor |
| SD0_CLK/SD0_CMD/SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); includes internal pull-ups and drive strength control |
Key Features
| Feature | Design Value |
|---|---|
| Hardware-accelerated graphics | GLCDC + DRW2D enables real-time 2D vector drawing, bit blitting, and multi-plane LCD overlay without CPU load |
| Dual-bank flash with BGO | Allows background programming/erasing while executing from alternate bank-enabling seamless firmware updates |
| IEC60730-ready safety suite | Includes CRCA, IWDT windowing, self-diagnostic A/D, oscillation-stop detection, and register write protection |
| Event Link Controller (ELC) | 83 internal event sources can be chained across peripherals (e.g., timer → ADC → DMA → interrupt) with zero CPU latency |
| Secure boot & IP protection | Trusted Memory (TM) prevents read-out of protected code flash regions; TSIP provides hardware AES and key management |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time process visualization, alarm logging, and remote diagnostics via Ethernet. IC Role / Device Role / Timing Role: Primary application processor running RTOS, driving 480×272 LCD via GLCDC, capturing sensor data via S12AD, and communicating via CAN/Ethernet. Use Value: DRW2D accelerates UI rendering; dual-bank flash enables field-upgradable firmware; TSIP secures OTA update integrity. | Use Scenario: Protocol-convergent edge node aggregating Modbus RTU (via SCI), CANopen (via CAN), and MQTT (via Ethernet) for cloud telemetry. IC Role / Device Role / Timing Role: Central protocol translator with deterministic timing: CAN mailbox filtering, SCI baud rate generation, and Ethernet frame buffering via EDMAC. Use Value: ELC synchronizes CAN message arrival → SCI transmission → Ethernet packet assembly; 640 KB SRAM buffers multi-protocol payloads. |
| Secure IoT Edge Node | Medical Data Logger |
Use Scenario: Battery-powered patient monitor collecting ECG, SpO₂, and temperature, then encrypting and transmitting via TLS over Ethernet. IC Role / Device Role / Timing Role: Safety-certified controller performing analog acquisition (S12AD), cryptographic processing (TSIP/AES), and secure network stack execution. Use Value: IEC60730-compliant self-tests ensure runtime integrity; on-die temperature sensor validates thermal operating conditions. | Use Scenario: Portable diagnostic device recording multi-channel biomedical waveforms to SD card with timestamped metadata and CRC-protected logs. IC Role / Device Role / Timing Role: High-fidelity data acquisition engine using S12AD scan mode, SDHI high-speed writes, and RTC time-stamping with leap-year correction. Use Value: Dual A/D units enable simultaneous analog capture; SDHI supports 25 MB/s writes; RTC includes error compensation and time-capture on external trigger. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEDFBG#30 | Same RX65N Group, 144-pin LQFP (PLQP0144KA-B), 1 MB flash, 256 KB SRAM, no Ethernet MAC or GLCDC | Suitable for cost-sensitive, non-graphical industrial controls with CAN/SCI but no display or Ethernet requirements | Select when footprint size, BOM cost, and absence of graphics/Ethernet reduce system complexity |
| R5F566TEHGBG#20 | RX66T Group, same 176-pin LFBGA, 160 MHz, 2 MB flash, enhanced MTU3 for motor control, no SDHI/SDSI/GLCDC/DRW2D | Optimized for servo drives and inverters requiring high-resolution PWM, encoder interfaces, and fast current-loop response | Select when motor control precision and real-time PWM dead-time compensation outweigh HMI/SD needs |
Compared with R5F565NEHGBG#20, R5F565NEDFBG#30 reduces integration (no Ethernet/GLCDC) for lower cost and smaller footprint, while R5F566TEHGBG#20 trades HMI peripherals for advanced motor control timing-making R5F565NEHGBG#20 optimal for display-rich, protocol-diverse edge nodes where graphics, storage, and security coexist.
Availability
R5F565NEHGBG#20 is available at Aetrix Electronics and suitable for industrial HMI panels, smart gateway controllers, secure IoT edge nodes, and medical data loggers requiring stable component supply, long-term lifecycle support, and automotive-grade reliability under extended temperature operation.
Supply support for R5F565NEHGBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX65N Group-including R5F565NEHGBG#20-is designed for high-integration industrial edge devices requiring rich connectivity (Ethernet/CAN/SD), real-time graphics (GLCDC/DRW2D), and functional safety (IEC60730).
FAQ
What is the maximum operating frequency and CPU architecture of the R5F565NEHGBG#20?
The R5F565NEHGBG#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core with 5-stage pipeline, variable-length instructions, and IEEE-754 single-precision FPU. It delivers 240 DMIPS and supports memory protection unit (MPU) enforcement for secure multitasking environments.
Does the R5F565NEHGBG#20 support Ethernet and CAN communication simultaneously?
Yes, the R5F565NEHGBG#20 integrates both a full-featured Ethernet MAC (10/100 Mbps MII/RMII) and two independent CAN modules compliant with ISO11898-1, each supporting 32 mailboxes. These operate concurrently with dedicated DMA engines (EDMAC and CAN TX/RX buffers), enabling protocol gateway applications without CPU bottleneck.
What graphics and display capabilities does the R5F565NEHGBG#20 provide?
The R5F565NEHGBG#20 includes a Graphic-LCD Controller (GLCDC) supporting multiple LCD panel types and resolutions, plus a 2D Drawing Engine (DRW2D) for hardware-accelerated vector drawing, bit blitting, rotation, and scaling. Together they enable real-time UI rendering on displays up to WVGA resolution without burdening the RXv2 core.
How does the R5F565NEHGBG#20 meet IEC60730 Class B safety requirements?
The R5F565NEHGBG#20 meets IEC60730 Class B through integrated features including oscillation-stop detection, CRC calculator (CRCA), independent watchdog timer (IWDT) with windowing, self-diagnostic A/D converter, register write protection, and Trusted Secure IP (TSIP) for secure boot validation-all documented in Renesas' Functional Safety Manual R01UM0059EJ0200.
What is the flash and RAM configuration of the R5F565NEHGBG#20?
The R5F565NEHGBG#20 features 2 MB of on-chip code flash memory with dual-bank architecture enabling background programming and seamless bank switching, plus 640 KB of high-speed SRAM (256 KB main + 384 KB expansion) operating at full 120 MHz with zero wait states.
R5F565NEHGBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NEHGBG#20 FAQ
1.How can I place an order for R5F565NEHGBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NEHGBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NEHGBG#20 reliable?
The price and inventory of R5F565NEHGBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NEHGBG#20 is usually 5 days.
3.What payment methods are accepted for R5F565NEHGBG#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NEHGBG#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NEHGBG#20?
R5F565NEHGBG#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NEHGBG#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NEHGBG#20?
For technical support, including R5F565NEHGBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NEHGBG#20 requirements.
6.How does Aetrix verify that R5F565NEHGBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NEHGBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NEHGBG#20 meets industry standards.
7.What is the process for return or replacement of R5F565NEHGBG#20?
All R5F565NEHGBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NEHGBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NEHGBG#20 part is unused and in its original packaging.
Return procedure for R5F565NEHGBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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