Renesas R5F565NEHGFC#30
- Part No.:
- R5F565NEHGFC#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F565NEHGFC#30.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,419
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Product details
Overview
R5F565NEHGFC#30 from Renesas is a 32-bit RXv2 microcontroller operating at up to 120 MHz (240 DMIPS), featuring on-chip FPU, 2 MB code flash with dual-bank support, 640 KB SRAM, Ethernet MAC, CAN, SD host/slave, QSPI, and hardware AES-128/192/256 encryption - deployed in industrial HMI, networked gateway, and secure IoT edge devices.
For engineers reviewing the R5F565NEHGFC#30 datasheet, R5F565NEHGFC#30 pinout, R5F565NEHGFC#30 application, or R5F565NEHGFC#30 equivalent, key selection criteria include its 176-pin LFBGA package, -40°C to +105°C extended temperature grade (G-version), integrated GLCDC + DRW2D for display control, and IEC60730-compliant safety features including CRC, IWDT, and register write protection.
Technical Context
The R5F565NEHGFC#30 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions, supporting IEEE-754 single-precision floating-point arithmetic and two MAC units. Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator, enabling independent domain clocking (ICLK up to 120 MHz, PCLKA up to 120 MHz, PCLKB up to 60 MHz).
It integrates dual 12-bit A/D converters (8 + 21 channels), two 12-bit D/A channels, temperature sensor, RTC with battery backup, and security IP including TSIP and AES engines. Peripheral interconnect uses Event Link Controller (ELC) for CPU-free signal chaining across 83 internal event sources, reducing interrupt latency and software overhead.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC with 5-stage pipeline, 240 DMIPS @ 120 MHz |
| Max Operating Frequency | 120 MHz system clock (ICLK); supports no-wait flash access up to 50 MHz |
| Memory | 2 MB code flash (dual-bank), 640 KB SRAM (256 KB + 384 KB expansion), 32 KB data flash (100k erase cycles) |
| Analog Peripherals | Dual 12-bit S12AD (8 + 21 ch), 2× R12DA, on-die temperature sensor (±1°C) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), 2× CAN (ISO 11898-1), 3× RSPI, 1× QSPI, 3× RIIC (up to 1 Mbps), 13× SCI |
| Security & Safety | AES-128/192/256, TSIP, MPU (8 regions), CRC calculator (8/32-bit), IWDT with window function, register write protection |
| Display & Imaging | GLCDC (3-plane overlay), DRW2D (vector/bit-blit), PDC (CMOS camera interface) |
| Package & Temp | LFBGA-176 (13 × 13 mm, 0.8 mm pitch), G-grade: –40°C to +105°C |
Pinout & Package
Package: PLBG0176GA-A - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 13 mm × 13 mm body, 0.8 mm ball pitch, RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/analog power domains (2.7–3.6 V); separate AVCC pins enable noise-isolated analog operation |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin cell or supercapacitor |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for high-accuracy system timing and Ethernet clock derivation |
| MD0 / MD1 | Mode setting pins | Determine boot mode (single-chip, SCI/USB/FINE boot) and endian configuration at reset release |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MDIO/MDC interface for configuring external Ethernet PHY |
| ETXD0–ETXD3 / ETXCK / ERXD0–ERXD3 / ERXCK | Ethernet physical layer I/O | MII interface signals; RMII mode uses subset (ETXD0/ETXCK/ERXD0/ERXDV/ERXCK) |
| SD0CMD / SD0CLK / SD0D0–SD0D3 | SD host interface bus | 4-bit SD bus supporting SD memory and SDIO cards up to 25 MB/s (high-speed mode) |
| CAN0TX / CAN0RX / CAN1TX / CAN1RX | CAN transceiver I/O | Differential signaling pairs per channel; require external CAN transceivers for bus connection |
| QSPI_IO0–QSPI_IO3 / QSPI_CLK / QSPI_CS | Quad SPI interface | Supports x1/x2/x4 I/O modes for serial NOR flash; enables execute-in-place (XIP) from external memory |
| GLCD_D0–GLCD_D23 / GLCD_HSYNC / GLCD_VSYNC / GLCD_DE | Graphic LCD controller outputs | 24-bit RGB parallel interface with sync signals; drives TFT panels up to WXGA resolution |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Secure IP (TSIP) | Hardware-accelerated AES, SHA, RSA, ECC, and key management - enables secure boot and OTA firmware updates without software crypto overhead |
| Event Link Controller (ELC) | 83 internal event sources routed without CPU intervention - e.g., TPU output triggers A/D conversion or GLCDC frame sync triggers DRW2D rendering start |
| Dual-Bank Flash Architecture | Enables background programming while executing from alternate bank - critical for fail-safe field firmware updates in industrial gateways |
| IEC60730 Class B Support | Integrated oscillation-stop detection, CRC calculator, IWDT with window, self-diagnostic A/D, and register write protection - reduces external safety component count |
| Graphics Acceleration | DRW2D engine performs vector drawing and bit-blit operations with bus-master DMA - offloads CPU for UI rendering in HMI applications |
| Flexible Clock Domain Control | Independent PCLKA (120 MHz), PCLKB (60 MHz), PCLKC/D (60 MHz) domains allow optimized peripheral clocking - e.g., Ethernet and USB run at full speed while ADC runs at lower jitter-sensitive rate |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled factory operator interface with real-time process visualization and alarm logging. IC Role / Device Role / Timing Role: Main application processor running RTOS, driving 800×480 TFT via GLCDC+DRW2D, sampling analog sensors via dual S12AD, and communicating over CAN/Ethernet. Use Value: Integrated graphics acceleration eliminates external GPU; dual-bank flash enables seamless firmware updates without panel downtime. | Use Scenario: Protocol-convergent gateway aggregating Modbus RTU, CANopen, and EtherNet/IP traffic into MQTT/HTTPS cloud uplinks. IC Role / Device Role / Timing Role: Central protocol translator with Ethernet MAC, dual CAN, multiple SCI/RSPI interfaces, and TLS offload via TSIP. Use Value: Hardware AES and SHA accelerate TLS handshake; ELC synchronizes CAN message timestamping with Ethernet packet transmission. |
| Networked Medical Device | Smart Building Controller |
Use Scenario: UL-certified patient monitor with wired Ethernet connectivity, local display, and encrypted data storage. IC Role / Device Role / Timing Role: Safety-critical controller managing vital sign acquisition (S12AD), display (GLCDC), secure data logging (AES + data flash), and remote diagnostics (Ethernet + USB). Use Value: IEC60730-compliant peripherals and register write protection meet medical functional safety requirements without external watchdog co-processors. | Use Scenario: HVAC/BMS controller interfacing with temperature/humidity sensors, relay banks, and building management network (BACnet/IP or KNX). IC Role / Device Role / Timing Role: Real-time coordinator using RTC calendar functions, PWM fan control (MTU3), SDHI for log storage, and Ethernet for BACnet/IP stack. Use Value: Standby RAM preserves state during brownouts; 105°C rating ensures reliability in enclosed electrical cabinets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHDFC#30 | Same RX65N Group die, but 144-pin LQFP package (PLQP0144KA-B), 256 KB SRAM, 1 MB flash, -40°C to +85°C (D-grade) | Suitable for cost-sensitive, space-constrained designs without Ethernet or high-resolution display needs | Select when board layout favors QFP, thermal budget limits G-grade operation, or flash/SRAM requirements are lower |
| R5F566TEHDFC#30 | RX66T Group MCU, 160 MHz, enhanced MTU3 for motor control, no GLCDC/DRW2D, 1.5 MB flash, 384 KB SRAM | Optimized for servo/inverter control with encoder capture and complementary PWM dead-time compensation | Choose for motion control where display capability is unnecessary and higher PWM precision is required |
Compared with R5F565NEHGFC#30, the R5F565NEHDFC#30 trades display/security/performance for smaller footprint and lower cost, while the R5F566TEHDFC#30 shifts focus from graphics and networking to deterministic motor control - making R5F565NEHGFC#30 uniquely balanced for secure, connected, visual edge devices.
Availability
R5F565NEHGFC#30 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and networked medical devices requiring stable component supply, long-term lifecycle assurance, and extended temperature operation.
Supply support for R5F565NEHGFC#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.
The RX65N Group, including R5F565NEHGFC#30, was designed specifically for secure, connected industrial edge applications requiring rich human-machine interaction, real-time communication, and functional safety compliance - bridging the gap between general-purpose MCUs and application-specific processors.
FAQ
What is the maximum operating frequency and core type of the R5F565NEHGFC#30?
The R5F565NEHGFC#30 operates at a maximum frequency of 120 MHz using the 32-bit RXv2 CPU core. It delivers 240 DMIPS performance and includes single-precision IEEE-754 floating-point unit, two MAC units, and 32-bit multiplier with one-cycle execution. The core implements CISC Harvard architecture with five-stage pipeline and variable-length instructions for ultra-compact code density.
Does the R5F565NEHGFC#30 support Ethernet and CAN simultaneously?
Yes, the R5F565NEHGFC#30 integrates one Ethernet MAC (10/100 Mbps, MII/RMII) and two independent CAN channels (ISO 11898-1 compliant, 32 mailboxes each). Both interfaces operate concurrently with dedicated DMA controllers (EDMACa for Ethernet, CAN module for CAN), and their clocks are independently configurable - enabling simultaneous protocol handling in gateway or automation applications without resource contention.
What display capabilities does the R5F565NEHGFC#30 provide?
The R5F565NEHGFC#30 includes a Graphic-LCD Controller (GLCDC) supporting 24-bit RGB parallel output with HSYNC/VSYNC/DE signals, and a 2D Drawing Engine (DRW2D) for vector drawing and bit-blit operations. It supports three overlay planes, multiple pixel formats (32/16/8 bpp), and CLUT-based color lookup. These features enable direct drive of WXGA-resolution TFT panels without external graphics ICs in industrial HMI designs.
How does the R5F565NEHGFC#30 support functional safety standards like IEC60730?
The R5F565NEHGFC#30 includes multiple hardware features for IEC60730 Class B compliance: oscillation-stop detection, CRC calculator (8/32-bit), independent watchdog timer (IWDT) with window function, self-diagnostic A/D converter, and register write protection. These are documented in Renesas' RX65N Functional Safety Manual (R01UM0125EJ0200) and eliminate need for external safety monitors in many certified designs.
What is the package type and temperature grade of the R5F565NEHGFC#30?
The R5F565NEHGFC#30 uses the PLBG0176GA-A package: a 176-ball LFBGA with 13 mm × 13 mm body and 0.8 mm ball pitch. It is rated for the extended industrial temperature range of –40°C to +105°C (G-grade), making it suitable for deployment in harsh environments such as factory floors, outdoor gateways, and enclosed control cabinets where thermal management is constrained.
R5F565NEHGFC#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NEHGFC#30 FAQ
1.How can I place an order for R5F565NEHGFC#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NEHGFC#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NEHGFC#30 reliable?
The price and inventory of R5F565NEHGFC#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NEHGFC#30 is usually 5 days.
3.What payment methods are accepted for R5F565NEHGFC#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NEHGFC#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NEHGFC#30?
R5F565NEHGFC#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NEHGFC#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NEHGFC#30?
For technical support, including R5F565NEHGFC#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NEHGFC#30 requirements.
6.How does Aetrix verify that R5F565NEHGFC#30 is sourced from the original manufacturer or authorized distributors?
All R5F565NEHGFC#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NEHGFC#30 meets industry standards.
7.What is the process for return or replacement of R5F565NEHGFC#30?
All R5F565NEHGFC#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NEHGFC#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NEHGFC#30 part is unused and in its original packaging.
Return procedure for R5F565NEHGFC#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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