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Renesas R5F565NEHGLK#20
- Part No.:
- R5F565NEHGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F565NEHGLK#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:416
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Product details
Overview
R5F565NEHGLK#20 from Renesas is a 120-MHz 32-bit RXv2 core MCU with single-precision IEEE-754 FPU, 240 DMIPS performance, 2 Mbyte on-chip code flash (dual-bank), 640 Kbyte SRAM, and integrated Ethernet MAC, CAN, SD host/slave, QSPI, GLCDC, DRW2D, and TSIP encryption. It serves as a high-integration application processor for industrial HMI, networked gateways, and secure edge controllers operating from 2.7–3.6 V.
For engineers reviewing the R5F565NEHGLK#20 datasheet, R5F565NEHGLK#20 pinout, R5F565NEHGLK#20 application, or R5F565NEHGLK#20 equivalent, key selection criteria include its 177-pin TFLGA package (8 × 8 mm, 0.5-mm pitch), -40°C to +105°C G-grade temperature range, dual-bank flash for safe firmware updates, hardware-accelerated AES/TSIP, and real-time peripheral support including 2× CAN channels, 13× SCI, 3× I²C, and 2× 12-bit D/A converters.
Technical Context
The R5F565NEHGLK#20 implements the RXv2 CPU core with Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and IWDT-dedicated oscillator, with independent domain clocks (ICLK up to 120 MHz, PCLKA up to 120 MHz, PCLKB up to 60 MHz) enabling precise peripheral timing control.
It features a full-featured safety subsystem including MPU (8 regions), Trusted Memory (TM) for code protection, register write protection, CRCA for CRC-8/32, and IEC60730-compliant self-diagnostic functions for A/D converter, oscillation-stop detection, and frequency measurement - all supporting functional safety certification in industrial applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard architecture with 5-stage pipeline and 240 DMIPS @ 120 MHz |
| Operating Frequency | Max 120 MHz system clock (ICLK); supports no-wait flash access up to 50 MHz or cache-hit at 120 MHz |
| Memory | 2 Mbyte dual-bank code flash (background programming), 32 Kbyte data flash (100k erase cycles), 640 Kbyte SRAM (no wait states) |
| Analog Peripherals | Two 12-bit A/D units (8 + 21 channels), two 12-bit D/A channels, on-chip temperature sensor (±1°C) |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), 2× CAN (ISO11898-1, 32 mailboxes/channel), 13× SCI, 3× I²C (up to 1 Mbps), QSPI, SDHI/SDSI, MMCIF |
| Graphics & Imaging | Graphic-LCD controller (GLCDC) with 3-plane overlay, 2D drawing engine (DRW2D) with vector/bit-blit acceleration, parallel data capture (PDC) for CMOS camera |
| Security & Safety | Hardware AES (128/192/256-bit), Trusted Secure IP (TSIP), MPU, Trusted Memory (TM), CRCA, IEC60730 diagnostic suite |
Pinout & Package
Package: TFLGA-177 (PTLG0177KA-A), 8 × 8 mm, 0.5-mm pitch, 136 general-purpose I/O pins (19 with 5-V tolerance), 1 dedicated input pin, pull-up and open-drain configurable per pin.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Separate digital/analog domains; AVCC0/AVCC1 power S12AD units and internal regulators |
| VBATT | Battery backup supply | Enables RTC operation during main power loss; connects to coin-cell or backup source |
| RES# | Active-low reset input | Asynchronous hardware reset; low pulse ≥ 100 ns initiates full chip reset sequence |
| CLKIN / CLKOUT | External crystal interface | Supports 8–24 MHz crystal or ceramic resonator for main clock oscillator (MOSC) |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3-compliant MDIO bus for configuring external Ethernet PHY |
| ETXD0–ETXD3 / ERXD0–ERXD3 | Ethernet data lines | MII mode: 4-bit TX/RX data; RMII mode: multiplexed to 2-bit TX/RX + REF_CLK |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating runtime interruption |
| Trusted Secure IP (TSIP) | Hardware-accelerated cryptographic engine supporting AES, SHA, RSA, ECC, and key management with tamper-resistant key storage |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - e.g., TPU output triggers A/D conversion or GPIO toggle |
| GLCDC + DRW2D co-processing | Offloads GUI rendering: GLCDC handles display timing and plane composition; DRW2D accelerates vector drawing and bit-blit operations |
| IEC60730 Class B compliance support | Integrated diagnostics: oscillation-stop detection, CRC calculator (CRCA), A/D self-test, register write protection, and memory test routines |
Applications
| Industrial HMI Panels | Secure IoT Gateways |
|---|---|
Use Scenario: Touch-enabled factory operator interface with local graphics rendering and remote data upload via Ethernet/CAN. IC Role / Device Role / Timing Role: Primary application processor managing GLCDC-driven LCD, DRW2D-accelerated UI, real-time CAN bus monitoring, and encrypted Ethernet telemetry. Use Value: Dual-bank flash enables over-the-air firmware updates without halting HMI operation; TSIP secures cloud communication keys and firmware signatures. | Use Scenario: Edge gateway aggregating sensor data from Modbus RTU, CANopen, and BLE peripherals before forwarding to cloud via TLS-secured Ethernet. IC Role / Device Role / Timing Role: Central protocol translator and security anchor - runs multiple concurrent stacks (CAN, SCI-based Modbus, TCP/IP) with hardware crypto offload. Use Value: Integrated AES/TSIP eliminates need for external secure element; 2× CAN channels support dual-network redundancy; SDHI enables local firmware/log storage. |
| Networked Building Controllers | Medical Data Loggers |
Use Scenario: HVAC controller with BACnet/IP over Ethernet, LonWorks/CAN fieldbus, and local SD card logging. IC Role / Device Role / Timing Role: Real-time deterministic controller synchronizing HVAC actuator PWM (via MTU3), environmental A/D sampling, and time-stamped network packet generation. Use Value: PCLKA-synchronized MTU3 delivers jitter-free 3-phase complementary PWM for inverter drives; RTC with battery backup maintains accurate timestamps across power cycles. | Use Scenario: Portable patient monitor recording ECG, temperature, and SpO₂ with encrypted local storage and USB host upload to clinical PC. IC Role / Device Role / Timing Role: Signal acquisition hub - 12-bit S12ADFa samples analog biosignals, R12DA drives reference DACs, USBb provides certified host interface. Use Value: On-chip temperature sensor calibrates A/D offset drift; dual 12-bit D/A channels generate precision reference waveforms; USBb complies with USB-IF certification requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F565NEHGLK#30 | Same die, identical specs, but rated for -40°C to +85°C (D-grade) instead of +105°C (G-grade) | Suitable for non-extended temperature environments; lower thermal margin in enclosed enclosures | Select #30 only when ambient operating temperature remains ≤85°C and cost optimization is prioritized |
| R5F566NEHGLK#20 | Same package and pinout, but with 1.5 Mbyte flash, 256 Kbyte SRAM, and no GLCDC/DRW2D graphics subsystem | Lacks integrated LCD controller and 2D accelerator - requires external GPU or simpler display interface | Choose for cost-sensitive applications needing Ethernet/CAN connectivity but no local graphics rendering |
Compared with R5F565NEHGLK#20, the #30 variant trades extended temperature capability for lower cost in benign environments, while the R5F566NEHGLK#20 reduces memory and removes graphics IP to serve headless industrial controllers - neither is pin-compatible drop-in replacement due to differing thermal and feature sets.
Availability
R5F565NEHGLK#20 is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, networked building controllers, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F565NEHGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX65N Group - including R5F565NEHGLK#20 - was designed for high-performance, safety-certifiable industrial applications demanding integrated connectivity (Ethernet/CAN), graphics (GLCDC/DRW2D), and hardware security (TSIP) in a single chip.
FAQ
What is the maximum operating frequency and core type of the R5F565NEHGLK#20?
The R5F565NEHGLK#20 features a 32-bit RXv2 CPU core with a maximum operating frequency of 120 MHz, delivering 240 DMIPS performance. It supports single-precision IEEE-754 floating-point arithmetic and includes a 5-stage pipeline with variable-length instructions for high code density. The R5F565NEHGLK#20 achieves no-wait-state flash access up to 50 MHz or at 120 MHz when ROM cache hits occur.
Does the R5F565NEHGLK#20 support dual-bank flash for firmware updates?
Yes, the R5F565NEHGLK#20 includes a dual-bank code flash architecture enabling background programming. This allows the R5F565NEHGLK#20 to execute code from one bank while simultaneously erasing and programming the other, ensuring zero downtime during over-the-air or field firmware updates - a critical capability for industrial and medical systems requiring continuous operation.
What graphics and display capabilities does the R5F565NEHGLK#20 provide?
The R5F565NEHGLK#20 integrates a Graphic-LCD Controller (GLCDC) supporting 3-plane overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) with vector drawing (lines, triangles, circles) and bit-blit acceleration (copy, stretch, rotate). These enable rich GUI rendering directly on the R5F565NEHGLK#20 without external GPU, supporting resolutions up to WXGA and color depths including 32-/16-bpp graphics and CLUT-based palettes.
How does the R5F565NEHGLK#20 support functional safety standards like IEC60730?
The R5F565NEHGLK#20 includes dedicated hardware for IEC60730 Class B compliance: oscillation-stop detection, CRCA for CRC-8/32, A/D converter self-diagnostic function, register write protection, and memory test support. These features are documented in Renesas' Functional Safety Manual for the RX65N Group and allow developers to implement certified safety routines without external components - essential for R5F565NEHGLK#20-based appliance and industrial control designs.
What is the package type and pin count of the R5F565NEHGLK#20?
The R5F565NEHGLK#20 uses a 177-pin TFLGA package (PTLG0177KA-A), measuring 8 × 8 mm with 0.5-mm pitch. It provides 136 general-purpose I/O pins (19 with 5-V tolerance), 1 dedicated input pin, and configurable pull-up/open-drain per pin. This compact, fine-pitch land-grid array supports high-density PCB layouts while maintaining signal integrity for Ethernet, CAN, and high-speed interfaces.
R5F565NEHGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX65N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, LINbus, MMC/SD, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F565NEHGLK#20 FAQ
1.How can I place an order for R5F565NEHGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F565NEHGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F565NEHGLK#20 reliable?
The price and inventory of R5F565NEHGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F565NEHGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F565NEHGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F565NEHGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F565NEHGLK#20?
R5F565NEHGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F565NEHGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F565NEHGLK#20?
For technical support, including R5F565NEHGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F565NEHGLK#20 requirements.
6.How does Aetrix verify that R5F565NEHGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F565NEHGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F565NEHGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F565NEHGLK#20?
All R5F565NEHGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F565NEHGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F565NEHGLK#20 part is unused and in its original packaging.
Return procedure for R5F565NEHGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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