Renesas R5F56604BGFB#10
- Part No.:
- R5F56604BGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F56604BGFB#10.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,838
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F56604BGFB#10 from Renesas is a 32-bit RXv3 core MCU operating at up to 120 MHz, featuring 1 Mbyte on-chip code flash, 128 Kbytes SRAM, 32 Kbytes data flash, CAN FD interface, 12-bit A/D and D/A converters, RTC with sub-clock oscillator support, and 134 general-purpose I/O pins in a 144-pin LFQFP package. It targets industrial control, motor drive, and safety-critical embedded systems requiring IEC60730 compliance.
For engineers reviewing the R5F56604BGFB#10 datasheet, R5F56604BGFB#10 pinout, R5F56604BGFB#10 application, or R5F56604BGFB#10 equivalent, key selection criteria include its 120-MHz real-time performance (709 CoreMark), integrated FPU for floating-point math, dual 12-bit DACs usable as comparator references, CAN FD compliance per ISO 11898-1:2015, and hardware safety features including MPU, Trusted Memory, CRC calculator, and clock accuracy monitoring.
Technical Context
The R5F56604BGFB#10 implements the RXv3 CPU core with single-cycle instruction execution, 32×32→64-bit multiplier, 32/32→32-bit divider, and IEEE 754-compliant single-precision FPU. Its clock system integrates main (8–24 MHz crystal), sub-clock (32.768 kHz), and on-chip oscillators (LOCO/HOCO/IWDT-dedicated), with independent PLL and frequency-division paths for ICLK (up to 120 MHz), PCLKA (120 MHz), PCLKB (60 MHz), PCLKD (60 MHz), and BCLK (40 MHz).
Peripheral integration includes MTU3a (9-channel 16/32-bit timer with complementary PWM and dead-time control), 24-channel S12ADH A/D converter (0.9 µs min conversion time at 60 MHz ADCLK), R12DAb dual 12-bit D/A, CMPC 4-channel analog comparator, REMCa remote control receiver, and ELC for interrupt-free inter-module event linking - enabling deterministic low-latency operation in sleep modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 709 CoreMark, IEEE 754 FPU, 113 instructions |
| Memory | 1 Mbyte code flash (no-wait at 120 MHz), 32 Kbyte data flash (100k erase cycles), 128 Kbyte SRAM (no-wait) |
| Analog Peripherals | 24-channel 12-bit S12ADH ADC (0.9 µs/ch), dual 12-bit R12DAb DACs, 4-channel CMPC comparator |
| Timers & Control | MTU3a (9 channels), TMRb (4 ch), CMT/CMTW (8 ch total), IWDT + WDTA, RTC with sub-clock support |
| Communication | CAN FD (ISO 11898-1:2015), 13 SCI channels (async/sync/I²C/SPI/LIN), 2 RIIC, 1 RSPI (30 Mbps), REMCa |
| Package & Environment | PLQP0144KA-B (144-pin LFQFP, 20×20 mm, 0.5 mm pitch), G-version (−40°C to +105°C), 2.7–5.5 V supply |
| Safety Features | MPU (8 regions), Trusted Memory (TM), CRCA (8/32-bit CRC), CAC, DOCA, register write protection |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.5 mm pitch, exposed thermal pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 | Power supply input | Core/analog supply (2.7–5.5 V); AVCC0 must be ≥ VCC and within 3.0–5.5 V range |
| RES# | Active-low reset input | Hardware reset assertion; internal POR/LVD also generates reset when VCC drops below threshold |
| XTAL / EXTAL | Main clock oscillator terminals | Connects to 8–24 MHz crystal; enables PLL reference for 120 MHz system clock |
| RTCXTAL / RTCXTAL | Sub-clock oscillator terminals | Connects to 32.768 kHz crystal; required for RTC and deep software standby mode operation |
| TXD0 / RXD0 | SCI0 serial interface | Asynchronous UART interface; supports LIN, smart card, and clock-synchronous modes via SCIk |
| CTX0 / CRX0 | CAN FD channel 0 | Differential CAN FD transceiver interface compliant with ISO 11898-1:2015 (standard/extended frames) |
| AD00–AD23 | Analog input channels | 24 dedicated pins for S12ADH; support self-diagnosis and analog input disconnection detection |
| DA0 / DA1 | Digital-to-analog outputs | Two 12-bit voltage outputs (0–AVCC0); usable as reference inputs for CMPC comparators |
| PO00–PO133 | General-purpose I/O | 134 programmable ports with 5-V tolerance, open-drain, pull-up, and switchable drive strength |
Key Features
| Feature | Design Value |
|---|---|
| Floating-point unit (FPU) | IEEE 754 single-precision hardware accelerator enabling deterministic real-time math for motor control and signal processing |
| Event Link Controller (ELC) | 83 internal event signals routed without CPU intervention - e.g., MTU trigger → A/D conversion → DMA transfer in deep software standby |
| Trusted Memory (TM) | Code flash region protected against read-out; only CPU instruction fetch allowed - critical for secure boot and IP protection |
| Complementary PWM with dead-time | MTU3a hardware auto-inserts non-overlapping delays for 3-phase inverter gate drive - eliminates software timing errors |
| IEC60730 safety support | Integrated oscillation-stop detection, RAM test assist (DOC), CRC calculator, clock accuracy monitor (CAC), and register write protection |
Applications
| Industrial Motor Drive | Building Automation Controller |
|---|---|
Use Scenario: Closed-loop vector control of 3-phase BLDC/PMSM motors in HVAC compressors and pumps. IC Role / Device Role / Timing Role: Real-time computation engine executing FOC algorithms, generating complementary PWM with hardware dead-time, sampling current/voltage via 24-channel ADC, and communicating over CAN FD. Use Value: Deterministic 120 MHz execution ensures <1 µs current loop response; dual DACs provide precise reference voltages for analog comparator-based overcurrent protection. | Use Scenario: Central controller managing lighting, HVAC, access, and fire alarm subsystems across multi-floor commercial buildings. IC Role / Device Role / Timing Role: System-on-chip host processor running RTOS, interfacing with multiple sensor networks (I²C, RS485 via SCI), storing configuration in data flash, and maintaining accurate time via RTC with battery-backed sub-clock. Use Value: 134 GPIOs enable direct connection to diverse peripherals; 128 KB SRAM supports concurrent protocol stacks; IEC60730 features satisfy functional safety requirements for Class B equipment. |
| Smart Energy Metering | Factory Automation I/O Module |
Use Scenario: DIN-rail mounted polyphase electricity meter with harmonic analysis, tamper detection, and DLMS/COSEM communication. IC Role / Device Role / Timing Role: High-precision metrology processor acquiring voltage/current waveforms via 24-channel ADC, computing RMS/power harmonics using FPU, and transmitting data over RS485 (SCI) and RF (via REMCa or external transceiver). Use Value: 0.9 µs ADC conversion time enables >16 kHz sampling for Class 0.2 accuracy; 32 KB data flash stores 30+ days of billing logs with 100k erase endurance. | Use Scenario: Distributed digital I/O module connecting PLC fieldbus (CAN FD) to 32-channel isolated digital inputs and 16-channel relay outputs. IC Role / Device Role / Timing Role: Fieldbus gateway with CAN FD physical layer interface, high-speed GPIO scanning, and deterministic event-triggered response via ELC-linked timers and interrupts. Use Value: Hardware ELC eliminates CPU polling overhead - input state changes directly trigger output updates or CAN message transmission within <100 ns jitter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F56605BGFB#10 | Same RX660 Group, identical 144-pin LFQFP package and peripheral set, but with 512 Kbyte code flash instead of 1 Mbyte | Suitable where firmware size <512 KB and cost optimization is prioritized over future firmware expansion headroom | Select R5F56605BGFB#10 only if application firmware fits within 512 KB and long-term code growth is not anticipated. |
| R5F56607BGFB#10 | Same package and flash/RAM capacity, but includes JTAG debug interface (R5F56604BGFB#10 has FINE-only; JTAG omitted per Table 1.2) | Required for legacy JTAG-based production programming or third-party debugger compatibility not supported by FINE | Choose R5F56607BGFB#10 only if JTAG infrastructure is mandatory; otherwise R5F56604BGFB#10 offers identical runtime functionality at lower cost. |
Compared with R5F56605BGFB#10, the R5F56604BGFB#10 provides double code flash capacity for complex control algorithms or OTA update partitions; versus R5F56607BGFB#10, it trades JTAG for cost reduction while retaining full FINE debug capability and identical real-time performance, safety features, and peripheral integration.
Availability
R5F56604BGFB#10 is available at Aetrix Electronics and suitable for industrial motor drives, building automation controllers, and smart energy metering systems requiring stable component supply, extended temperature operation (−40°C to +105°C), and long-term lifecycle support.
Supply support for R5F56604BGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX660 Group - including R5F56604BGFB#10 - is engineered for high-integrity industrial applications demanding real-time determinism, functional safety (IEC60730), and rich analog/motor control peripherals in a single chip.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F56604BGFB#10?
The R5F56604BGFB#10 operates at a maximum frequency of 120 MHz and achieves 709 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's single-cycle instruction execution, 32×32→64-bit hardware multiplier, and zero-wait-state access to 1 Mbyte code flash and 128 Kbyte SRAM - all confirmed in the R01DS0393EJ0100 datasheet Rev.1.00.
Does the R5F56604BGFB#10 support CAN FD, and what standard does it comply with?
Yes, the R5F56604BGFB#10 integrates a CAN FD module compliant with ISO 11898-1:2015, supporting both standard and extended frames. It operates at data rates up to 5 Mbps in FD mode and maintains full backward compatibility with classical CAN 2.0B - verified in Section 1.1 and Table 1.1 of the official datasheet.
What analog peripherals are integrated into the R5F56604BGFB#10?
The R5F56604BGFB#10 integrates a 24-channel 12-bit S12ADH A/D converter (0.9 µs minimum conversion time), two 12-bit R12DAb D/A converters (0–AVCC0 output), and four-channel CMPC analog comparators. The DAC outputs can serve as precision reference voltages for the comparators - all detailed in Sections 1.1 and Table 1.1 of the R01DS0393EJ0100 datasheet.
Is the R5F56604BGFB#10 qualified for extended temperature operation?
Yes, the R5F56604BGFB#10 is the G-version device rated for −40°C to +105°C operation. This is explicitly stated in Table 1.1 (Page 9) and confirmed by the "G" in the part number per Table 1.3 of the R01DS0393EJ0100 datasheet Rev.1.00.
What debugging interfaces does the R5F56604BGFB#10 support?
The R5F56604BGFB#10 supports the FINE (single-wire) debugging interface only - JTAG is omitted in this variant per Table 1.2 of the R01DS0393EJ0100 datasheet. FINE enables full debug, flash programming, and boundary scan functionality with minimal pin count, making it ideal for space-constrained industrial designs.
R5F56604BGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 133
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 24x12b; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F56604BGFB#10 FAQ
1.How can I place an order for R5F56604BGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F56604BGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F56604BGFB#10 reliable?
The price and inventory of R5F56604BGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F56604BGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F56604BGFB#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F56604BGFB#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F56604BGFB#10?
R5F56604BGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F56604BGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F56604BGFB#10?
For technical support, including R5F56604BGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F56604BGFB#10 requirements.
6.How does Aetrix verify that R5F56604BGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F56604BGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F56604BGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F56604BGFB#10?
All R5F56604BGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F56604BGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F56604BGFB#10 part is unused and in its original packaging.
Return procedure for R5F56604BGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F56604BGFB#10 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

