Renesas R5F56604GGFB#10
- Part No.:
- R5F56604GGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F56604GGFB#10.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F56604GGFB#10 from Renesas is a 32-bit RXv3 microcontroller with 120 MHz maximum operating frequency, 1 Mbyte on-chip code flash, 128 Kbytes SRAM, and integrated CAN FD, 12-bit A/D and D/A converters, RTC, and remote control signal receiver - deployed in industrial motor control, building automation gateways, and IEC 60730-compliant appliance controllers.
For engineers reviewing the R5F56604GGFB#10 datasheet, R5F56604GGFB#10 pinout, R5F56604GGFB#10 application, or R5F56604GGFB#10 equivalent, key selection criteria include its G-version (–40°C to +105°C) temperature rating, PLQP0144KA-B 144-pin LFQFP package with JTAG/FINE debug support, 120-MHz real-time performance (709 CoreMark), and full CAN FD compliance per ISO 11898-1:2015.
Technical Context
The R5F56604GGFB#10 implements the RXv3 CPU core with single-cycle instruction execution, IEEE 754-compliant single-precision FPU, and 16-register bank save for fast context switching. Its clock system integrates main (8–24 MHz crystal), sub-clock (32.768 kHz), and on-chip oscillators (LOCO/HOCO/IWDT-dedicated), with independent PLL and frequency-division paths for ICLK (up to 120 MHz), PCLKA (120 MHz), PCLKB (60 MHz), and ADCLK (60 MHz).
Peripheral coordination is managed via the Event Link Controller (ELC), enabling 83 internal event signals to trigger timer operations, A/D conversions, or GPIO state changes without CPU intervention. Safety-critical functions include MPU-based memory protection, Trusted Memory (TM) for code flash read protection, CRC calculator (CRCA) with configurable polynomials, and hardware-accelerated self-diagnostic features for A/D input disconnection and oscillator stoppage detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 709 CoreMark, single-cycle instruction execution |
| Memory | 1 Mbyte code flash (no-wait at 120 MHz), 32 Kbyte data flash (100k erase cycles), 128 Kbyte SRAM (no-wait) |
| Operating Voltage | 2.7–5.5 V supply (VCC), 3.0–5.5 V analog (AVCC0), supports 5-V-tolerant I/O on 4 pins |
| Temperature Range | G-version: –40°C to +105°C - qualified for extended industrial and automotive under-hood applications |
| Communication | CAN FD (ISO 11898-1:2015), 13 SCI channels (async/sync/SmartCard/SPI/I²C), 2 RIIC (400 kbps), 1 RSPI (30 Mbps) |
| Analog Peripherals | 24-channel 12-bit S12ADH (0.9 µs min conversion), 2-channel 12-bit R12DAb (0–AVCC0 output), 4-channel CMPC |
| Timers & Control | MTU3a (9 channels), TMRb (4×8-bit), CMT/CMTW (8×16/2×32-bit), IWDT (dedicated 120-kHz clock), RTCC with time capture |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.5 mm pitch, lead-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0 | Power supply inputs | Core/analog domain supplies; AVCC0 must be ≥ VCC and within 3.0–5.5 V for A/D/D/A operation |
| RES#, RESET | Reset input | Active-low asynchronous reset; triggers nine distinct reset sources including POR, LVD, and deep software standby release |
| XTAL, EXTAL | Main clock oscillator interface | Connects to 8–24 MHz crystal; enables PLL reference for 120 MHz system clock generation |
| RTCXTAL, RTCEXTAL | Sub-clock oscillator interface | Connects to 32.768 kHz crystal; required for RTCC calendar/timekeeping and deep software standby RTC operation |
| TMS, TDI, TDO, TCK | JTAG debug interface | IEEE 1149.1-compliant boundary-scan and debug access; supports full-speed emulation and flash programming |
| FINE | Single-wire debug interface | Reduces debug footprint vs. JTAG; supports program download, breakpoint, and register access during development |
| TXDn, RXDn | SCI serial I/O | Asynchronous UART pins for up to 13 SCI channels; configurable for LIN, smart-card, SPI, or I²C modes |
| CANFD_TX, CANFD_RX | CAN FD transceiver interface | Differential pair supporting ISO 11898-1:2015 standard/extended frames at up to 5 Mbps data phase |
| AD0–AD23 | A/D converter inputs | 24 dedicated analog input pins; support programmable sampling time, group scan priority, and digital comparison |
| DA0, DA1 | D/A converter outputs | 2 buffered voltage outputs (0–AVCC0); usable as reference for CMPC comparators or external analog circuitry |
Key Features
| Feature | Design Value |
|---|---|
| ELC-driven peripheral chaining | 83 internal event signals enable timer-triggered A/D conversion or GPIO toggling without CPU wake-up - critical for low-power deterministic response |
| Trusted Memory (TM) protection | Hardware-enforced read-protection of designated code flash regions; only CPU instruction fetch allowed - prevents firmware extraction in secure boot designs |
| IEC 60730 safety support | Integrated oscillation-stop detection, RAM test assist (DOC), CRCA, clock accuracy monitoring (CAC), and register write protection - reduces external safety component count |
| Multi-clock domain architecture | Independent ICLK (120 MHz), PCLKA (120 MHz), PCLKB (60 MHz), ADCLK (60 MHz), and BCLK (40 MHz) domains allow optimized power/performance partitioning per subsystem |
| Remote control signal receiver (REMC) | Hardware-accelerated IR protocol decoding with 8-byte buffer and 4-pattern matching (header/data0/data1/special) - eliminates CPU polling in HVAC and appliance remotes |
Applications
| Industrial Motor Drive Controller | Building Automation Gateway |
|---|---|
Use Scenario: Closed-loop control of 3-phase BLDC/PMSM motors in HVAC compressors and industrial pumps using space-vector PWM. IC Role / Device Role / Timing Role: Main controller executing FOC algorithms via RXv3 FPU, generating complementary PWM via MTU3a with automatic dead-time insertion, and sampling current/voltage via S12ADH. Use Value: 120 MHz real-time processing enables <1 µs current loop update; CAN FD provides deterministic 5 Mbps fieldbus communication to PLCs and HMIs. | Use Scenario: Protocol translation hub aggregating Modbus RTU, BACnet MS/TP, and KNX devices into Ethernet/IP or MQTT networks. IC Role / Device Role / Timing Role: Dual-role processor: SCI/RSPI handles legacy fieldbus physical layers while TCP/IP stack runs on embedded RTOS; ELC synchronizes packet timestamping with RTC. Use Value: Integrated CAN FD, 13 SCI channels, and 2 RIIC interfaces eliminate external bus bridges; 128 KB SRAM supports concurrent multi-protocol stacks. |
| IEC 60730-Certified Appliance MCU | Automotive Body Control Module (BCM) |
Use Scenario: Safety-monitored control unit in washing machines, dishwashers, and refrigerators requiring Class B compliance per IEC 60730. IC Role / Device Role / Timing Role: Primary MCU executing control logic while concurrently running hardware self-tests: CAC verifies clock accuracy, CRCA validates flash integrity, DOC tests RAM, and IWDT enforces watchdog independence. Use Value: On-chip safety peripherals reduce certification effort; TM-protected bootloader prevents unauthorized firmware updates; G-temp rating ensures reliability in hot appliance enclosures. | Use Scenario: Centralized lighting, window lift, and door lock control in entry-level vehicles with CAN FD backbone. IC Role / Device Role / Timing Role: CAN FD node managing distributed actuators; uses REMC for factory programming via IR; leverages 5-V-tolerant I/O for direct connection to 12 V sensors/switches. Use Value: Single-chip solution replaces discrete CAN transceivers and level shifters; –40°C to +105°C rating meets automotive ambient requirements; 32 KB data flash stores calibration and diagnostic logs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F56605GDFB#10 | Same RX660 Group, identical 144-pin LFQFP package and 120 MHz CPU, but 512 KB code flash (vs. 1 MB) and no sub-clock oscillator (RTCC disabled) | Suitable for cost-sensitive designs omitting RTC/calendar functions and requiring lower flash density | Select when RTC, deep software standby, or 32.768 kHz timekeeping are unnecessary - reduces BOM cost without sacrificing core compute or CAN FD capability |
| R5F56606GDFB#10 | Same package and flash/SRAM capacity, but lacks JTAG interface (FINE-only debug); sub-clock oscillator present (RTCC enabled) | Targeted at production units where JTAG is needed only during development, not in-field service | Choose for volume production where debug footprint reduction and RTCC functionality are prioritized over JTAG-based in-system programming and boundary-scan testing |
Compared with R5F56604GGFB#10, the R5F56605GDFB#10 trades flash capacity and RTC support for lower cost, while the R5F56606GDFB#10 retains full memory but removes JTAG - making the R5F56604GGFB#10 the optimal choice when full debug visibility, maximum code storage, and certified real-time clock operation are simultaneously required.
Availability
R5F56604GGFB#10 is available at Aetrix Electronics and suitable for industrial motor control, building automation gateways, and IEC 60730-compliant appliance controllers requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for R5F56604GGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT applications - with over 40 years of microcontroller innovation and ISO/TS 16949-certified manufacturing.
The RX660 Group, including R5F56604GGFB#10, is engineered for high-integrity industrial control systems demanding real-time determinism, functional safety (IEC 60730), and multi-protocol connectivity - bridging the gap between general-purpose MCUs and application-specific ASSPs.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F56604GGFB#10?
The R5F56604GGFB#10 operates at a maximum frequency of 120 MHz and achieves 709 CoreMark points under benchmark conditions. This performance stems from the RXv3 CPU core's single-cycle instruction execution, 32-bit multiplier/divider, barrel shifter, and IEEE 754-compliant FPU - all verified in the official Renesas datasheet R01DS0393EJ0100. The R5F56604GGFB#10 sustains this speed with zero wait states on both 1 Mbyte code flash and 128 Kbyte SRAM.
Does the R5F56604GGFB#10 support CAN FD, and what standard does it comply with?
Yes, the R5F56604GGFB#10 integrates a fully compliant CAN FD module supporting both standard and extended frames per ISO 11898-1:2015. It delivers up to 5 Mbps data-phase transfer rates and includes hardware message filtering, FIFO buffering, and error confinement - confirmed in the peripheral specification table of R01DS0393EJ0100. The R5F56604GGFB#10 requires an external CAN transceiver for physical layer interfacing.
What package type and pin count does the R5F56604GGFB#10 use?
The R5F56604GGFB#10 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package with 20 × 20 mm body size and 0.5 mm pitch. This package includes JTAG and FINE debug interfaces, sub-clock oscillator pins (RTCXTAL/RTCEXTAL), and 130 general-purpose I/O pins - as specified in Table 1.2 of the RX660 Group datasheet R01DS0393EJ0100. The 'G' in the part number denotes the –40°C to +105°C temperature grade.
How does the R5F56604GGFB#10 support IEC 60730 functional safety compliance?
The R5F56604GGFB#10 includes hardware features essential for Class B IEC 60730 compliance: oscillation-stop detection, clock frequency accuracy measurement (CAC), CRC calculator (CRCA), independent watchdog timer (IWDT) with window function, RAM test-assist via DOC, and register write protection. These are documented in Section 1.1 and safety chapter of R01DS0393EJ0100. The R5F56604GGFB#10 enables developers to implement required self-tests without external components - reducing system complexity and certification effort.
What are the key analog peripherals integrated into the R5F56604GGFB#10?
The R5F56604GGFB#10 integrates a 24-channel 12-bit A/D converter (S12ADH) with 0.9 µs minimum conversion time at 60 MHz ADCLK, two 12-bit D/A converters (R12DAb) with 0–AVCC0 output range, four analog comparators (CMPC), and an on-die temperature sensor (±1.0°C). All analog blocks support ELC triggering and self-diagnostic functions like analog input disconnection detection - detailed in Sections 1.1 and 23–26 of R01DS0393EJ0100. The R5F56604GGFB#10 uses these for closed-loop control, sensor conditioning, and thermal monitoring.
R5F56604GGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX600
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 130
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 24x12b; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F56604GGFB#10 FAQ
1.How can I place an order for R5F56604GGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F56604GGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of R5F56604GGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F56604GGFB#10 is usually 5 days.
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For technical support, including R5F56604GGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F56604GGFB#10 requirements.
6.How does Aetrix verify that R5F56604GGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F56604GGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F56604GGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F56604GGFB#10?
All R5F56604GGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F56604GGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F56604GGFB#10 part is unused and in its original packaging.
Return procedure for R5F56604GGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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