Renesas R5F566NDDDBG#20
- Part No.:
- R5F566NDDDBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F566NDDDBG#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:152
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Product details
Overview
R5F566NDDDBG#20 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 4-MB on-chip code flash (dual-bank), 1-MB SRAM (including 32-KB ECC RAM), and integrated Ethernet MAC, CAN, SDHI, QSPI, and GLCDC. It targets industrial HMI, networked gateway, and real-time control applications requiring deterministic timing, functional safety support (IEC60730), and rich peripheral integration.
For engineers reviewing the R5F566NDDDBG#20 datasheet, R5F566NDDDBG#20 pinout, R5F566NDDDBG#20 application, or R5F566NDDDBG#20 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-C (176-pin LFBGA), validated pin functions, real-world use cases, and two confirmed alternative MCUs - all grounded in Renesas' official R01DS0344EJ0120 Rev.1.20 documentation.
Technical Context
The R5F566NDDDBG#20 implements the RXv3 CPU core with 698 CoreMark at 120 MHz, supporting little-endian or big-endian data, 113 instructions including DSP and floating-point ops, and collective register bank save across 16 banks. Its memory subsystem includes dual-bank 4-MB flash (8.3-ns access at 120 MHz), 512-KB main SRAM, 512-KB expansion RAM, and 32-KB ECC RAM with SEC-DED error correction.
Peripherals are clocked via independent domains: ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/DRW2D/GLCDC, PCLKB up to 60 MHz for timers/A/D converters, and BCLK up to 80 MHz for external bus. It integrates three CAN channels (ISO11898-1, 32 mailboxes each), one Ethernet MAC with RMII/MII, and hardware-accelerated DRW2D graphics engine with vector drawing and bit blitting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision FPU (IEEE-754) |
| Memory | 4-MB code flash (dual-bank, background programming), 1-MB SRAM (512-KB main + 512-KB expansion), 32-KB ECC RAM |
| Timers | 4×32-bit GPTW, 9×16-bit MTU3a, 6×16-bit TPUa, 2×32-bit CMTW, RTC with battery backup |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), 3×CAN (ISO11898-1), 13×SCI, 3×I²C (up to 1 Mbps), 1×QSPI, 1×SDHI (25 MB/s) |
| Analog | Two 12-bit A/D units (8 + 21 channels), 2×12-bit D/A, on-chip temperature sensor |
| Security & Safety | Optional TSIP encryption (AES-128/192/256), IEC60730-compliant self-test, MPU, register write protection |
| Package | PLQP0176KB-C: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, –40°C to +85°C (D-version) |
Pinout & Package
Package: PLQP0176KB-C - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm body, 0.5-mm ball pitch, lead-free, RoHS-compliant. Thermal pad exposed on underside for enhanced heat dissipation in high-performance operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog domain supplies (2.7–3.6 V); separate AVCC pins ensure clean analog reference for ADC/DAC |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/clock retention without system reset |
| XTAL, EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; required for precise Ethernet/USB timing and RTC accuracy |
| MD0–MD2 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and operating mode (single-chip/ROM-enabled extended) at reset release |
| ETH_MDC, ETH_MDIO | PHY management interface | Enable hardware-managed PHY configuration via PMGI; offloads CPU from MDIO register polling |
| ETXD0–ETXD3, ERXD0–ERXD3 | Ethernet MAC data lines | 4-bit nibble interface for RMII; supports 10/100 Mbps full/half-duplex with flow control (IEEE 802.3x) |
| CAN0_TX, CAN0_RX | Channel 0 CAN transceiver I/O | Differential signaling compliant with ISO11898-1; supports standard/extended frames and 32-mailbox FIFO |
| SD0_CMD, SD0_CLK, SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting SD Memory Card v3.01 and SDIO v3.00; enables direct firmware updates and data logging |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating runtime interruption |
| Hardware-accelerated DRW2D engine | Offloads CPU from 2D graphics rendering - supports vector drawing, bit blitting, rotation, and CLUT-based color conversion |
| Integrated GLCDC with 3-plane overlay | Drives graphic LCDs up to 1024×768; overlays background, graphic 1, and graphic 2 layers with alpha blending |
| Event Link Controller (ELC) | Direct hardware interconnection of 123 internal events (e.g., timer overflow → ADC trigger → DMA transfer) without CPU intervention |
| IEC60730-compliant safety features | Includes oscillation-stop detection, CRC-A, IWDT windowing, A/D self-diagnostic, and register write protection for Class B certification |
Applications
| Industrial HMI Gateway | Smart Building Controller |
|---|---|
|
Use Scenario: Central controller aggregating Modbus RTU sensors, managing local display via GLCDC, and forwarding data over Ethernet to cloud platform. IC Role / Device Role / Timing Role: Main application processor executing real-time task scheduler, driving 800×480 TFT-LCD via GLCDC+DRW2D, and handling TCP/IP stack on Ethernet MAC. Use Value: Dual-bank flash allows OTA firmware updates without interrupting HMI responsiveness; 1-MB SRAM buffers video frame data and protocol stacks simultaneously. |
Use Scenario: HVAC zone controller integrating temperature/humidity sensors, actuating valves via PWM, and communicating via CAN bus to central BMS. IC Role / Device Role / Timing Role: Real-time control unit running PID loops at 10-ms intervals, generating complementary PWM for 3-phase inverters via MTU3a, and managing CAN mailbox arbitration. Use Value: Complementary PWM with automatic dead-time insertion prevents shoot-through in motor drives; 32-mailbox CAN buffer handles bursty BMS traffic without packet loss. |
| Networked Medical Device | Secure Edge IoT Node |
|
Use Scenario: Portable diagnostic device acquiring ECG signals via 12-bit ADC, storing waveform data to SD card, and transmitting encrypted reports via Ethernet. IC Role / Device Role / Timing Role: Signal acquisition controller synchronizing ADC sampling (0.48 µs/channel), buffering raw data in ECC RAM, and encrypting payloads using TSIP AES-256 before transmission. Use Value: SEC-DED ECC RAM ensures data integrity during long-term waveform storage; TSIP accelerates encryption without consuming CPU cycles or exposing keys in software. |
Use Scenario: Field-deployed sensor node collecting environmental data, performing edge analytics, and uploading results via secure TLS tunnel over Ethernet. IC Role / Device Role / Timing Role: Secure embedded host running FreeRTOS, executing lightweight ML inference on DRW2D-accelerated buffers, and managing certificate-based TLS handshake via hardware crypto assist. Use Value: Hardware AES and TRNG (via TSIP) enable fast, side-channel-resistant key generation and session encryption - critical for zero-trust deployment models. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566NEDDBG#20 | Same RX66N family, identical 176-pin LFBGA (PLQP0176KB-C), but with 2-MB code flash instead of 4-MB; same peripherals, clocking, and ECC RAM. | Suitable where firmware size < 2 MB and cost sensitivity outweighs future scalability needs. | Select R5F566NEDDBG#20 only if application binary fits within 2-MB flash and no dual-bank update requirement exists. |
| R5F566TDDDBG#20 | Same package and flash size, but belongs to RX66T group - optimized for motor control with enhanced MTU3a PWM resolution, 3-phase complementary outputs, and faster current-sampling ADC triggers. | Better suited for servo/inverter drives; lacks GLCDC, DRW2D, SDHI, and Ethernet MAC present in R5F566NDDDBG#20. | Choose R5F566TDDDBG#20 only when motor control performance dominates over HMI/networking requirements. |
Compared with R5F566NDDDBG#20, the R5F566NEDDBG#20 reduces flash capacity by half but retains identical peripheral set and safety features - ideal for cost-constrained deployments without field-upgrade needs. The R5F566TDDDBG#20 trades networking and graphics capability for higher-resolution PWM and motor-specific timing - making it unsuitable for gateway or display-centric designs.
Availability
R5F566NDDDBG#20 is available at Aetrix Electronics and suitable for industrial HMI, smart building controllers, and networked medical devices requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F566NDDDBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RX66N Group - including the R5F566NDDDBG#20 - was designed for high-integration industrial applications demanding real-time performance, functional safety, rich connectivity (Ethernet/CAN/SD), and advanced graphics capability in a single chip.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566NDDDBG#20?
The R5F566NDDDBG#20 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under those conditions. This performance stems from the RXv3 CPU core's efficient instruction pipeline, double-precision FPU, and zero-wait-state access to 4-MB flash and 1-MB SRAM - enabling deterministic execution for real-time industrial tasks.
Does the R5F566NDDDBG#20 support dual-bank flash for firmware updates?
Yes, the R5F566NDDDBG#20 supports dual-bank flash architecture, allowing background programming of one bank while executing code from the other. This enables safe, uninterrupted over-the-air (OTA) firmware updates - a critical capability for deployed industrial gateways and medical devices where downtime is unacceptable.
What package type and pin count does the R5F566NDDDBG#20 use?
The R5F566NDDDBG#20 uses the PLQP0176KB-C package: a 176-pin Low-Profile Fine-Pitch Ball Grid Array measuring 24 mm × 24 mm with 0.5-mm ball pitch. It is rated for –40°C to +85°C operation (D-version) and includes an exposed thermal pad for thermal management in high-throughput applications.
Which communication interfaces are integrated into the R5F566NDDDBG#20?
The R5F566NDDDBG#20 integrates Ethernet MAC (10/100 Mbps, MII/RMII), three CAN 2.0B channels (ISO11898-1), 13 serial channels (SCIj/i/h), three I²C interfaces (up to 1 Mbps), one QSPI, one SD host interface (SDHI), and one MMCIF. These interfaces support simultaneous wired connectivity for industrial protocols, human-machine interaction, and data storage.
Is the R5F566NDDDBG#20 qualified for functional safety standards like IEC60730?
Yes, the R5F566NDDDBG#20 includes multiple hardware features certified for IEC60730 Class B compliance: oscillation-stop detection, CRC-A accelerator, windowed independent watchdog timer (IWDTa), A/D converter self-diagnostic, and register write protection. These are documented in Renesas' Functional Safety Manual (R01UM0127EJ0200) and supported by safety libraries.
R5F566NDDDBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX66N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566NDDDBG#20 FAQ
1.How can I place an order for R5F566NDDDBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566NDDDBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566NDDDBG#20 reliable?
The price and inventory of R5F566NDDDBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566NDDDBG#20 is usually 5 days.
3.What payment methods are accepted for R5F566NDDDBG#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566NDDDBG#20 transactions.
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R5F566NDDDBG#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566NDDDBG#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566NDDDBG#20?
For technical support, including R5F566NDDDBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566NDDDBG#20 requirements.
6.How does Aetrix verify that R5F566NDDDBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F566NDDDBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566NDDDBG#20 meets industry standards.
7.What is the process for return or replacement of R5F566NDDDBG#20?
All R5F566NDDDBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566NDDDBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566NDDDBG#20 part is unused and in its original packaging.
Return procedure for R5F566NDDDBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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