Renesas R5F566NNDDFP#10
- Part No.:
- R5F566NNDDFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F566NNDDFP#10.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:720
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F566NNDDFP#10 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 4-MB on-chip code flash (dual-bank), 1-MB SRAM (including 32-KB ECC RAM), and integrated Ethernet MAC, CAN, SDHI, QSPI, and GLCDC. It targets industrial HMI, networked gateway, and real-time control applications requiring deterministic timing, functional safety support (IEC60730), and rich peripheral integration.
For engineers reviewing the R5F566NNDDFP#10 datasheet, R5F566NNDDFP#10 pinout, R5F566NNDDFP#10 application, or R5F566NNDDFP#10 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-C (176-pin LQFP, 24 × 24 mm, 0.5-mm pitch), validated pin functions, real-world use cases, and two confirmed alternative parts with documented technical and application differences.
Technical Context
The R5F566NNDDFP#10 implements the RXv3 CPU core with 698 CoreMark at 120 MHz, double-precision FPU, MPU, and collective register bank save for fast context switching. Its memory subsystem includes 4-MB dual-bank flash (8.3-ns access at 120 MHz), 1-MB SRAM (no wait states), 32-KB ECC RAM (SEC-DED), and 8-KB standby RAM backed by VBATT.
Peripheral architecture integrates Ethernet MAC + RMII/MII PHY interface, three CAN channels (32 mailboxes each), 13 SCI channels (asynchronous/smart-card/SPI/I²C modes), 3 RSPI, 1 QSPI, SDHI (25 MB/s), MMCIF (30 MB/s), PDC for CMOS camera, GLCDC + DRW2D for graphics acceleration, and dual 12-bit A/D converters (29 total channels).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision IEEE-754 FPU |
| Flash Memory | 4 Mbytes code flash with dual-bank structure enabling background programming and safe firmware updates |
| RAM | 1 Mbyte SRAM (no wait states), 32 Kbytes ECC RAM (SEC-DED), 8 Kbytes standby RAM |
| Peripherals | Ethernet MAC + RMII/MII, 3× CAN (ISO11898-1), SDHI (25 MB/s), QSPI, GLCDC + DRW2D, 2× 12-bit A/D (29 ch) |
| Package | PLQP0176KB-C: 176-pin LQFP, 24 × 24 mm, 0.5-mm pitch, 136 I/O pins, 19× 5-V tolerant |
| Operating Range | –40°C to +85°C (D-version), single 2.7–3.6 V supply, four low-power modes including deep software standby |
| Functional Safety | IEC60730-compliant features: oscillation-stop detection, CRC accelerator, IWDT, A/D self-diagnostic, register write protection |
Pinout & Package
Package: PLQP0176KB-C - 176-pin Low-profile Quad Flat Package, 24 mm × 24 mm body, 0.5 mm pitch, exposed thermal pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | 2.7–3.6 V main supply; separate analog domains enable clean ADC reference and RTC operation |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/timekeeping in deep software standby mode |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; enables precise clock source for Ethernet, USB, and real-time applications |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and operating mode (single-chip/on-chip ROM enabled/disabled) at reset release |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3u-compliant MII/RMII management bus for configuring external PHY without CPU overhead |
| ETXD0–ETXD3 / ETXEN / ETXER / ERXD0–ERXD3 / ERXDV / ERXER | Ethernet physical layer I/O | Direct RMII interface signals; eliminates need for external PHY transceiver in basic 10/100 Mbps implementations |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, with atomic bank swap on reset |
| Integrated GLCDC + DRW2D | Hardware-accelerated 2D graphics rendering and LCD panel driving-eliminates external GPU or display controller in HMI designs |
| SDHI + MMCIF dual host interfaces | Simultaneous support for SD memory cards (Ver. 3.01) and eMMC devices (JESD84-A441), enabling flexible storage expansion |
| IEC60730 safety peripherals | On-chip CRC accelerator, independent watchdog timer (IWDT), A/D self-test, and register lock mechanisms reduce certification effort |
| Event Link Controller (ELC) | 123 internal event sources routed without CPU intervention-enables deterministic, low-latency peripheral chaining (e.g., timer → ADC → DMA) |
Applications
| Industrial HMI Gateway | Smart Building Controller |
|---|---|
|
Use Scenario: Centralized building automation node aggregating Modbus RTU, CAN bus, and Ethernet/IP data from HVAC, lighting, and security subsystems. IC Role / Device Role / Timing Role: Real-time protocol gateway with deterministic interrupt latency (<1 µs), hardware-accelerated crypto (AES-128/192/256), and dual Ethernet ports via external switch. Use Value: Single-chip solution replaces MCU + FPGA + PHY stack; 136 GPIOs support direct sensor/actuator interfacing; 4-MB flash stores multiple firmware images and configuration databases. |
Use Scenario: Edge controller managing energy metering, occupancy sensing, and demand-response logic across distributed zones. IC Role / Device Role / Timing Role: Time-synchronized data logger using RTC with battery backup, 12-bit A/D (29 ch) for analog sensor inputs, and SDHI for local data buffering. Use Value: Standby RAM preserves state during brownouts; ECC RAM ensures integrity of critical control algorithms; IEC60730 features satisfy UL 60730 Class B requirements. |
| Networked Motor Drive Interface | Medical Diagnostic Display Terminal |
|
Use Scenario: Field-oriented control (FOC) interface bridging motor encoder feedback, PWM generation, and EtherCAT master communication. IC Role / Device Role / Timing Role: Real-time motion controller with GPTW timers generating synchronized 3-phase PWM (dead-time configurable), MTU3A for encoder quadrature decoding, and Ethernet MAC for industrial networking. Use Value: Hardware timer cascading and ELC eliminate CPU polling; dual 12-bit A/D units sample current/voltage simultaneously at ≤0.48 µs/channel for closed-loop stability. |
Use Scenario: Portable ultrasound or patient monitor display unit requiring high-resolution graphics, touch interface, and secure data export. IC Role / Device Role / Timing Role: Graphics subsystem controller with GLCDC driving 800×480 RGB LCD, DRW2D accelerating UI rendering, and AES/TSIP for HIPAA-compliant DICOM encryption. Use Value: On-chip 2D engine offloads ARM Cortex-M host; 1-MB SRAM buffers full-frame image data; QSPI supports fast boot from external XIP flash. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566NEDDFP#10 | Same RX66N family, identical 176-pin LQFP package, but with 2-MB flash and 512-KB SRAM (vs. 4-MB/1-MB) | Suitable for cost-sensitive applications where firmware size <2 MB and RAM footprint <512 KB | Select when full 4-MB flash and 1-MB RAM are not required-reduces BOM cost without changing PCB layout |
| R5F566TNDDE#10 | 224-pin LFBGA package (182 I/O), same 4-MB flash/1-MB RAM, adds PDC for CMOS camera interface (excluded in 176-pin variants) | Required for vision-based applications needing parallel image capture; incompatible pinout and thermal profile | Choose only if camera interface is mandatory and board redesign is acceptable-no pin compatibility with R5F566NNDDFP#10 |
Compared with R5F566NNDDFP#10, R5F566NEDDFP#10 reduces memory capacity but maintains identical peripheral set and package, enabling drop-in replacement where firmware fits; R5F566TNDDE#10 expands I/O and adds PDC at the cost of package incompatibility and higher assembly complexity.
Availability
R5F566NNDDFP#10 is available at Aetrix Electronics and suitable for industrial HMI, smart building controllers, networked motor drives, and medical display terminals requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F566NNDDFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX66N Group is designed for high-performance, safety-aware industrial applications-integrating real-time processing, rich connectivity (Ethernet/CAN/SD), graphics acceleration, and IEC60730 compliance in a single chip.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566NNDDFP#10?
The R5F566NNDDFP#10 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's optimized pipeline, double-precision FPU, and zero-wait-state access to 4-MB flash and 1-MB SRAM-making it suitable for demanding real-time control and protocol processing tasks.
Does the R5F566NNDDFP#10 support Ethernet connectivity without an external PHY?
Yes, the R5F566NNDDFP#10 integrates an Ethernet MAC with RMII and MII interfaces. When paired with a compatible external PHY (e.g., LAN8720A), it supports 10/100 Mbps operation. The PMGI module handles PHY register access autonomously, reducing CPU load. However, a discrete PHY IC is still required for physical layer signaling-no integrated PHY is present on-die.
What package type and pin count does the R5F566NNDDFP#10 use?
The R5F566NNDDFP#10 uses the PLQP0176KB-C package: a 176-pin LQFP with 24 mm × 24 mm body size, 0.5 mm pitch, and exposed thermal pad. It provides 136 general-purpose I/O pins, 19 of which are 5-V tolerant-ideal for industrial interfacing with legacy sensors and actuators.
How does the R5F566NNDDFP#10 support functional safety standards like IEC60730?
The R5F566NNDDFP#10 includes dedicated hardware for IEC60730 Class B compliance: oscillation-stop detection, CRC accelerator (CRCA), independent watchdog timer (IWDT), A/D converter self-diagnostic, and register write protection. These features are documented in Renesas' Functional Safety Manual R01UM0591EJ0100 and reduce software validation effort for household and industrial appliances.
Can the R5F566NNDDFP#10 execute code directly from external QSPI flash?
No, the R5F566NNDDFP#10 does not support XIP (execute-in-place) from external QSPI flash. Its QSPI interface is configured for data transfer only-booting and code execution must occur from on-chip 4-MB flash. External QSPI is used for firmware storage, configuration tables, or asset files accessed via DMA or CPU reads.
R5F566NNDDFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX66N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566NNDDFP#10 FAQ
1.How can I place an order for R5F566NNDDFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566NNDDFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566NNDDFP#10 reliable?
The price and inventory of R5F566NNDDFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566NNDDFP#10 is usually 5 days.
3.What payment methods are accepted for R5F566NNDDFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566NNDDFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F566NNDDFP#10?
R5F566NNDDFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566NNDDFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566NNDDFP#10?
For technical support, including R5F566NNDDFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566NNDDFP#10 requirements.
6.How does Aetrix verify that R5F566NNDDFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F566NNDDFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566NNDDFP#10 meets industry standards.
7.What is the process for return or replacement of R5F566NNDDFP#10?
All R5F566NNDDFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566NNDDFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566NNDDFP#10 part is unused and in its original packaging.
Return procedure for R5F566NNDDFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F566NNDDFP#10 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

