Renesas R5F566NNDGFB#10
- Part No.:
- R5F566NNDGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F566NNDGFB#10.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,548
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Product details
Overview
R5F566NNDGFB#10 from Renesas is a 32-bit RXv3 microcontroller operating at 120 MHz with double-precision IEEE-754 FPU, 4 MB on-chip code flash, 1 MB SRAM (including 32 KB ECC RAM), and integrated Ethernet MAC, CAN, SDHI, QSPI, and GLCDC. It targets industrial HMI, networked gateway, and embedded vision applications requiring real-time control, secure connectivity, and graphics acceleration.
For engineers reviewing the R5F566NNDGFB#10 datasheet, R5F566NNDGFB#10 pinout, R5F566NNDGFB#10 application, or R5F566NNDGFB#10 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-C (176-pin LQFP), validated peripheral timing constraints, and confirmed alternative MCUs for migration or dual-sourcing - all grounded in Renesas R01DS0344EJ0120 Rev.1.20.
Technical Context
The R5F566NNDGFB#10 implements the RXv3 CPU core with 698 CoreMark @ 120 MHz, supporting little-endian data and instruction layout, 113 instructions including DSP and floating-point ops, and a 16-bank register save function for fast context switching. Its memory subsystem integrates dual-bank 4 MB flash (8.3 ns read cycle), 1 MB SRAM (no wait states), 32 KB data flash (100k erase cycles), and 8 KB standby RAM backed by VBATT.
Peripherals are clocked across four domains: ICLK (up to 120 MHz for CPU), PCLKA (120 MHz for ETHERC/GLCDC/DRW2D), PCLKB (60 MHz for TPU/MTU/CMT), and PCLKC/PCLKD (60 MHz for S12AD units). The device supports IEC60730 safety functions including CRC calculation, oscillation-stop detection, and A/D self-diagnosis - critical for certified industrial control designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision IEEE-754 FPU |
| Memory | 4 MB code flash (dual-bank), 1 MB SRAM (no wait), 32 KB data flash (100k cycles), 32 KB ECC RAM (SEC-DED) |
| Package & Pins | PLQP0176KB-C 176-pin LQFP, 0.5 mm pitch, 24 × 24 mm, 136 GPIO (19 5-V tolerant) |
| Connectivity | Ethernet MAC + RMII/MII PHY interface, 3× CAN (ISO11898-1), 13× SCI, 3× RIIC (1 Mbps), 1× QSPI, 1× SDHI (25 MB/s) |
| Analog & Timing | Two 12-bit S12AD units (8+21 ch), 2× 12-bit D/A, RTC with battery backup, 29 timers including GPTW/MTU3a/TPUa |
| Graphics & Vision | GLCDC (3-plane overlay), DRW2D (vector/bit-blit), PDC (CMOS camera interface), SSIE (2-channel audio) |
| Security & Safety | Optional TSIP/AES-128/192/256, IEC60730 compliance features (CRC, IWDT, A/D self-test, register write protection) |
Pinout & Package
Package: PLQP0176KB-C - 176-pin LQFP, 24 mm × 24 mm, 0.5 mm pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/analog power rails (2.7–3.6 V); separate AVCC domains enable noise-isolated ADC operation |
| VBATT | Battery backup supply | Provides power to RTC during main VCC dropout; enables calendar/timekeeping in deep software standby |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; required for precise Ethernet/USB timing and RTC calibration |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3u-compliant MDIO bus for configuring external PHY registers without CPU intervention |
| TXD0 / RXD0 | SCI0 asynchronous serial I/O | Dedicated UART pins for bootloader, debug console, or host communication; supports LIN via SCIh |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting SD memory/SDIO cards up to 25 MB/s; includes built-in CRC7/CRC16 error checking |
| QSPI_IO0–3 / QSPI_CLK / QSPI_CS | Quad SPI interface | Direct connection to quad-output serial flash; enables XIP (execute-in-place) and fast firmware updates |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables background programming while executing from alternate bank - critical for zero-downtime firmware updates |
| Ethernet + USB + CAN triple connectivity | Single-chip support for industrial protocol gateways (Modbus TCP over Ethernet, CANopen over CAN, USB CDC ACM) |
| GLCDC + DRW2D graphics engine | Hardware-accelerated 2D rendering and LCD panel driving - eliminates need for external GPU in HMI designs |
| IEC60730 safety suite | On-chip CRC accelerator, IWDT with windowing, A/D self-test, and register lock bits - reduces certification effort for Class B appliances |
| Event Link Controller (ELC) | 123 internal event sources routed without CPU involvement - enables deterministic timer-triggered ADC sampling or PWM sync |
| 136 GPIO with flexible configuration | 5-V tolerant on 19 pins, open-drain capable, pull-up programmable - simplifies interfacing with legacy 5V peripherals and sensors |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time status visualization and alarm logging. IC Role / Device Role / Timing Role: Primary application processor running FreeRTOS, driving 480×272 RGB LCD via GLCDC, capturing touch via SCI-based controller, and communicating via CAN to field devices. Use Value: Integrated DRW2D accelerates UI redraws; dual-bank flash allows silent OTA updates; 120 MHz CPU handles multitasking without external co-processor. |
Use Scenario: Edge node aggregating sensor data from Modbus RTU field devices and forwarding to cloud via Ethernet/WiFi bridge. IC Role / Device Role / Timing Role: Protocol translation hub with Ethernet MAC (100 Mbps), 3× CAN channels (ISO11898-1), and SDHI for local data buffering on SD card. Use Value: Hardware CRC and DMA-accelerated packet handling reduce CPU load; TSIP enables secure TLS handshake offload for encrypted cloud upload. |
| Embedded Vision System | Secure Network Appliance |
|
Use Scenario: Low-power machine vision module capturing VGA images from CMOS sensor and performing edge inference preprocessing. IC Role / Device Role / Timing Role: Image acquisition controller using PDC for parallel sensor interface, DRW2D for ROI cropping/resizing, and QSPI for loading neural net weights from flash. Use Value: PDC synchronizes to HSYNC/VSYNC for frame-accurate capture; 1 MB SRAM holds full VGA frame + inference buffers; no external memory required. |
Use Scenario: Industrial firewall or secure remote access terminal enforcing encrypted communications between OT and IT networks. IC Role / Device Role / Timing Role: Security-enforcement MCU with AES-256 encryption, TSIP key management, Ethernet MAC for dual-NIC bridging, and watchdog supervision of critical services. Use Value: On-chip TSIP isolates cryptographic keys from software stack; IWDT windowing prevents malicious firmware lockup; dual CAN/Ethernet enables air-gapped zone separation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566NNDFB#10 | Same RX66N group, identical 176-pin LQFP package, but 2 MB flash (vs. 4 MB) and 512 KB SRAM (vs. 1 MB) | Suitable for cost-sensitive HMI or gateway designs where firmware size < 2 MB and buffer requirements fit 512 KB RAM | Select when full 4 MB flash and 1 MB SRAM are not required - lower BOM cost with identical pinout and peripheral set |
| R5F566TKDFB#10 | RX66T group variant; same 176-pin LQFP, 120 MHz, but optimized for motor control with enhanced MTU3a PWM dead-time resolution and PFC support | Targeted at servo drives and inverters; lacks SDHI, GLCDC, DRW2D, and Ethernet MAC present in R5F566NNDGFB#10 | Choose only for motor-control-focused applications; not a functional substitute for HMI/gateway/vision use cases requiring graphics or storage interfaces |
Compared with R5F566NNDGFB#10, R5F566NNDFB#10 offers identical peripheral integration and pin compatibility at reduced memory capacity, while R5F566TKDFB#10 trades graphics, storage, and networking peripherals for higher-precision motor control features - making neither a drop-in replacement but viable alternatives within defined application boundaries.
Availability
R5F566NNDGFB#10 is available at Aetrix Electronics and suitable for industrial HMI, smart gateway, and embedded vision applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production programs.
Supply support for R5F566NNDGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX66N Group is designed for high-performance industrial applications demanding rich connectivity, graphics capability, functional safety, and secure firmware execution - targeting HMI, gateway, and vision systems where integration reduces system complexity and bill-of-materials cost.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566NNDGFB#10?
The R5F566NNDGFB#10 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under those conditions. This performance level is enabled by the RXv3 CPU core's 113-instruction set, dual-issue capability for certain operations, and zero-wait-state access to 4 MB on-chip flash and 1 MB SRAM - all confirmed in Renesas R01DS0344EJ0120 Rev.1.20 Section 1.1.
Does the R5F566NNDGFB#10 support Ethernet and CAN simultaneously, and what are the physical layer requirements?
Yes, the R5F566NNDGFB#10 integrates one Ethernet MAC (ETHERC) compliant with IEEE 802.3u (10/100 Mbps, MII/RMII) and three independent CAN channels (ISO11898-1). It requires an external PHY chip for Ethernet physical layer signaling and external CAN transceivers for each CAN bus - both connected via dedicated pins (ETH_MDC/MDIO, CAN0_TX/RX, etc.) as specified in the R5F566NNDGFB#10 pin assignment table.
What graphics and display capabilities does the R5F566NNDGFB#10 provide, and which interfaces do they use?
The R5F566NNDGFB#10 includes a Graphic-LCD Controller (GLCDC) supporting 3-plane overlay (background, graphic 1, graphic 2) and a 2D Drawing Engine (DRW2D) for vector drawing and bit blitting. These operate via dedicated RGB or LVDS output pins and support resolutions up to WVGA. Both modules are clocked by PCLKA and require no external video memory - their frame buffers reside in the on-chip 1 MB SRAM, as detailed in Section 1.1 of R01DS0344EJ0120.
Is the R5F566NNDGFB#10 qualified for industrial temperature range, and what safety certifications does it support?
Yes, the R5F566NNDGFB#10 is rated for the industrial temperature range of −40°C to +85°C (D-version). It includes hardware features required for IEC60730 Class B compliance, including oscillation-stop detection, CRC calculation unit, independent watchdog timer (IWDT) with windowing, A/D converter self-diagnostic function, and register write protection - all documented in the "Useful functions for IEC60730 compliance" section of the R5F566NNDGFB#10 datasheet.
What is the flash and RAM configuration of the R5F566NNDGFB#10, and how is ECC implemented?
The R5F566NNDGFB#10 contains 4 MB of on-chip code flash memory (dual-bank structure), 1 MB of general-purpose SRAM (zero wait states), 32 KB of data flash (100,000 erase cycles), and 32 KB of ECC-protected RAM implementing SEC-DED (single-error correction, double-error detection). The ECC RAM is physically distinct, clocked at PCLKA, and used for critical data structures - its error reporting is handled via dedicated interrupt vectors per R01DS0344EJ0120 Section 1.1.
R5F566NNDGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566NNDGFB#10 FAQ
1.How can I place an order for R5F566NNDGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566NNDGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566NNDGFB#10 reliable?
The price and inventory of R5F566NNDGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566NNDGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F566NNDGFB#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566NNDGFB#10 transactions.
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R5F566NNDGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566NNDGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566NNDGFB#10?
For technical support, including R5F566NNDGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566NNDGFB#10 requirements.
6.How does Aetrix verify that R5F566NNDGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F566NNDGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566NNDGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F566NNDGFB#10?
All R5F566NNDGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566NNDGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566NNDGFB#10 part is unused and in its original packaging.
Return procedure for R5F566NNDGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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