Renesas R5F566NNHDBG#20
- Part No.:
- R5F566NNHDBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F566NNHDBG#20.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:152
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Product details
Overview
R5F566NNHDBG#20 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 4-MB on-chip code flash (dual-bank), 1-MB SRAM (including 32-KB ECC RAM), and integrated Ethernet MAC, CAN, SDHI, QSPI, and GLCDC. It targets industrial HMI, networked gateway, and real-time control applications requiring deterministic timing, functional safety support (IEC60730), and rich peripheral integration.
For engineers reviewing the R5F566NNHDBG#20 datasheet, R5F566NNHDBG#20 pinout, R5F566NNHDBG#20 application, or R5F566NNHDBG#20 equivalent, key selection considerations include its 176-pin LFBGA package (PLQP0176KB-C), 2.7–3.6-V supply range, -40°C to +85°C operating temperature (D-version), dual-bank flash for safe firmware updates, and hardware-accelerated 2D graphics rendering via DRW2D.
Technical Context
The R5F566NNHDBG#20 implements the RXv3 CPU core with 698 CoreMark at 120 MHz, supporting little-endian or big-endian data arrangement and 113 instructions including DSP and floating-point operations. Its memory subsystem includes 4-MB code flash with 8.3-ns read cycle at full speed, 32-KB reprogrammable data flash (100K erase cycles), and 1-MB SRAM split into 512-KB general-purpose, 512-KB expansion, and 32-KB ECC-protected banks.
Peripheral integration centers on real-time I/O coordination: Ethernet MAC (10/100 Mbps, MII/RMII), three CAN channels (ISO11898-1, 32 mailboxes each), 13 SCI channels (asynchronous/smart-card/SPI/I²C modes), SDHI (25 MB/s), QSPI, and parallel camera interface (PDC). Clock management includes PLL, HOCO/LOCO oscillators, and independent IWDT with window function.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision FPU (IEEE-754) |
| Memory | 4-MB code flash (dual-bank), 32-KB data flash (100K cycles), 1-MB SRAM (512-KB + 512-KB + 32-KB ECC) |
| Package | PLQP0176KB-C: 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, 136 I/O pins |
| Operating Range | -40°C to +85°C (D-version), 2.7–3.6-V single supply, RTC battery backup via VBATT |
| Peripherals | Ethernet MAC (10/100 Mbps), 3× CAN, 13× SCI, SDHI, QSPI, GLCDC, DRW2D, PDC, S12AD (29-channel 12-bit ADC) |
| Security & Safety | TSIP optional AES-128/192/256, IEC60730 compliance features (oscillation detection, CRC, self-diagnostic A/D) |
Pinout & Package
Package: PLQP0176KB-C - 176-pin Low-Profile Quad Flat Ball Grid Array (LFBGA), 24 mm × 24 mm body, 0.5-mm ball pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Power supply inputs | Core/analog power domains (2.7–3.6 V); separate AVCC pins enable clean analog reference for ADC/DAC |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/timekeeping in deep software standby mode |
| RES# | Active-low reset input | Hardware reset assertion; synchronous release with internal POR/LVD logic |
| CLKIN / CLKOUT | External crystal oscillator interface | Supports 8–24 MHz crystal; drives main PLL for system clock generation |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3u-compliant MDIO bus for PHY register access and configuration |
| ETH_TXD[3:0] / ETH_RXD[3:0] | Ethernet physical layer signals | MII interface pins; support 10/100 Mbps full/half-duplex operation with flow control |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 Full-Speed interface | On-chip transceiver supports host/function/OTG; no external pull-up required |
| SD_CLK / SD_CMD / SD_DATA[3:0] | SD host interface signals | 1- or 4-bit SD bus; supports high-speed mode (25 MB/s) per SD Physical Layer Spec v3.01 |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables background programming and safe firmware updates without halting execution or losing real-time responsiveness |
| Hardware-accelerated 2D graphics (DRW2D) | Offloads CPU for vector drawing (lines/triangles/circles), bit blitting, rotation, and texture mapping in embedded GUIs |
| Integrated graphic-LCD controller (GLCDC) | Direct drive of RGB/TFT panels up to 1024×768; supports 3-layer superposition (background + 2 graphics planes) |
| Event Link Controller (ELC) | 123 internal event sources routed without CPU intervention-e.g., timer overflow triggers ADC conversion or PWM update |
| IEC60730 safety functions | Includes oscillation-stop detection, CRC-A, IWDT windowing, A/D self-test, and register write protection for Class B compliance |
Applications
| Industrial HMI Gateway | Networked Building Controller |
|---|---|
|
Use Scenario: Embedded panel PC in factory automation displaying real-time machine status, alarms, and recipe management via TFT LCD. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving GLCDC+DRW2D for UI rendering, and managing EtherCAT/Modbus TCP over Ethernet MAC. Use Value: Dual-bank flash enables seamless field firmware upgrades; 1-MB SRAM buffers video frame data; 120-MHz CPU sustains <10-ms UI response latency. |
Use Scenario: HVAC controller aggregating sensor data (temp/humidity/CO₂) and communicating via BACnet/IP over Ethernet to building management system. IC Role / Device Role / Timing Role: Real-time control hub with Ethernet MAC, 3× CAN for legacy equipment, and 29-channel ADC for analog sensor acquisition. Use Value: Integrated Ethernet + CAN eliminates external bridge ICs; IEC60730 features satisfy UL 60730 certification requirements. |
| Smart Energy Meter Gateway | Medical IoT Edge Node |
|
Use Scenario: Utility meter concentrator collecting AMI data from sub-meters via RS485 (SCI) and transmitting via Ethernet or cellular modem. IC Role / Device Role / Timing Role: Secure data aggregator with TSIP-enabled AES encryption, SDHI for local log storage, and QSPI for secure boot image storage. Use Value: Optional TSIP provides hardware-accelerated crypto for TLS handshake and firmware signature verification; 32-KB ECC RAM protects critical runtime variables. |
Use Scenario: Portable diagnostic device capturing ECG waveforms via analog front-end and streaming processed data to cloud via Wi-Fi module (connected via SDIO or SPI). IC Role / Device Role / Timing Role: Signal processing engine using S12AD (21-channel) for multi-lead acquisition, DRW2D for waveform display, and USB for PC connectivity. Use Value: 0.48-µs ADC conversion time ensures >2-MSPS aggregate sampling; 176-pin LFBGA fits compact PCB layout while providing ample I/O for sensor interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566NNDDBG#20 | Same RX66N group, identical 176-pin LFBGA package, but 2-MB code flash (vs. 4-MB) and 512-KB SRAM (vs. 1-MB) | Suitable for cost-sensitive designs where firmware size <2 MB and RAM footprint <512 KB | Select when full 4-MB flash and 1-MB SRAM are not required; reduces BOM cost without changing PCB layout |
| R5F566TNDDBG#20 | Same package and memory size, but lacks Ethernet MAC, GLCDC, DRW2D, and PDC; adds extra SCI and CAN channels | Better suited for serial protocol concentrators or motor control where graphics/Ethernet are unnecessary | Choose when Ethernet and display peripherals are unused-reduces power consumption and simplifies software stack |
Compared with R5F566NNHDBG#20, the R5F566NNDDBG#20 offers identical pinout and peripheral set at lower memory density, while R5F566TNDDBG#20 trades graphics/Ethernet for expanded serial connectivity-enabling optimized cost and power for non-HMI applications.
Availability
R5F566NNHDBG#20 is available at Aetrix Electronics and suitable for industrial HMI, networked building control, and smart energy metering applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F566NNHDBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX66N Group is designed for high-performance, safety-aware embedded systems demanding real-time responsiveness, rich connectivity (Ethernet/CAN/USB/SD), and advanced human-machine interface capabilities-including hardware-accelerated 2D graphics and LCD control.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566NNHDBG#20?
The R5F566NNHDBG#20 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's efficient pipeline, double-precision FPU, and zero-wait-state access to 4-MB code flash and 1-MB SRAM-enabling deterministic real-time execution in demanding industrial applications.
Does the R5F566NNHDBG#20 support dual-bank flash for firmware updates?
Yes, the R5F566NNHDBG#20 supports dual-bank flash architecture, allowing background programming of one bank while executing code from the other. This enables safe, atomic firmware updates without interrupting real-time operation-a critical capability for industrial gateways and medical devices requiring high uptime.
What display interfaces does the R5F566NNHDBG#20 integrate for HMI applications?
The R5F566NNHDBG#20 integrates a Graphic-LCD Controller (GLCDC) supporting RGB/TFT panels up to 1024×768 and a 2D Drawing Engine (DRW2D) for hardware-accelerated vector graphics, bit blitting, and texture mapping. These peripherals eliminate external GPU requirements and reduce CPU load in embedded GUI applications.
How many CAN channels and mailboxes does the R5F566NNHDBG#20 provide?
The R5F566NNHDBG#20 includes three independent CAN modules compliant with ISO11898-1, each supporting 32 message mailboxes. This enables robust multi-node communication in automotive diagnostics, industrial automation, and building control networks-without requiring external CAN controllers or transceivers.
Is the R5F566NNHDBG#20 qualified for IEC60730 Class B compliance?
Yes, the R5F566NNHDBG#20 includes dedicated hardware features for IEC60730 Class B compliance: oscillation-stoppage detection, CRC-A accelerator, independent watchdog timer (IWDT) with window function, self-diagnostic A/D converter test, and register write protection. These are documented in Renesas Application Note R01AN3917JJ0100.
R5F566NNHDBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX66N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566NNHDBG#20 FAQ
1.How can I place an order for R5F566NNHDBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566NNHDBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566NNHDBG#20 reliable?
The price and inventory of R5F566NNHDBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566NNHDBG#20 is usually 5 days.
3.What payment methods are accepted for R5F566NNHDBG#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566NNHDBG#20 transactions.
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R5F566NNHDBG#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566NNHDBG#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566NNHDBG#20?
For technical support, including R5F566NNHDBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566NNHDBG#20 requirements.
6.How does Aetrix verify that R5F566NNHDBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F566NNHDBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566NNHDBG#20 meets industry standards.
7.What is the process for return or replacement of R5F566NNHDBG#20?
All R5F566NNHDBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566NNHDBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566NNHDBG#20 part is unused and in its original packaging.
Return procedure for R5F566NNHDBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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