Renesas R5F566NNHDFB#30
- Part No.:
- R5F566NNHDFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F566NNHDFB#30.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 144LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:166
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F566NNHDFB#30 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 4-MB on-chip code flash (dual-bank), 1-MB SRAM (including 32-KB ECC RAM), and integrated Ethernet MAC, CAN, USB 2.0 FS, SDHI, QSPI, and GLCDC - designed for industrial HMI, networked gateway, and real-time control applications requiring deterministic timing and functional safety support.
For engineers reviewing the R5F566NNHDFB#30 datasheet, R5F566NNHDFB#30 pinout, R5F566NNHDFB#30 application, or R5F566NNHDFB#30 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-C (176-pin LQFP, 24 × 24 mm, 0.5-mm pitch), validated pin functions, IEC60730-compliant peripherals, and two confirmed alternative MCUs with documented functional and packaging differences.
Technical Context
The R5F566NNHDFB#30 implements the RXv3 CPU core with 698 CoreMark at 120 MHz, supporting little-endian or big-endian data arrangement, 113 instructions including DSP and floating-point ops, and collective register bank save across 16 banks. Its memory subsystem includes dual-bank 4-MB flash enabling background programming and bank-swapped boot, plus 1-MB SRAM with 32-KB ECC RAM for error detection/correction.
Peripherals are clocked across five domains: ICLK (up to 120 MHz for CPU), PCLKA (120 MHz for ETHERC/GLCDC/DRW2D), PCLKB (60 MHz for timers/SCI), PCLKC/PCLKD (60 MHz for A/D units), and FCLK (60 MHz for flash interface). Real-time capabilities include RTC with battery backup, independent watchdog (IWDTa) with window function, and ELC-driven event linking across 123 internal signals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision FPU (IEEE-754) |
| Memory | 4-MB code flash (dual-bank, BGO supported), 1-MB SRAM (no wait states), 32-KB ECC RAM (SEC-DED) |
| Connectivity | Ethernet MAC + RMII/MII PHY interface, 3× CAN (ISO11898-1), 13× SCI, 3× RIIC (1 Mbps), 1× QSPI, 1× SDHI (25 MB/s) |
| Analog | Two 12-bit A/D units (8 + 21 channels), 2× 12-bit D/A, on-chip temperature sensor |
| Timers & PWM | 4× GPTW (32-bit), 9× MTU3a (16/32-bit), 6× TPUa, 4× TMR, CMT/CMTW, POE3a/POEG for waveform output control |
| Security & Safety | Optional TSIP/AES-128/192/256, IEC60730 compliance features: oscillation-stop detection, CRC-A, self-diagnostic A/D, register write protection |
| Package | PLQP0176KB-C: 176-pin LQFP, 24 × 24 mm, 0.5-mm pitch, –40°C to +85°C (D-version) |
Pinout & Package
Package: PLQP0176KB-C - 176-pin Low-profile Quad Flat Package, 24 × 24 mm body, 0.5-mm lead pitch, exposed thermal pad, RoHS-compliant, rated for –40°C to +85°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog supplies (2.7–3.6 V); separate AVCC domains enable noise-isolated analog operation |
| RES#, RESET | Reset input/output | Active-low hardware reset; supports POR, LVD, and deep software standby release |
| XTAL, EXTAL | Main clock oscillator terminals | Supports 8–24 MHz crystal/resonator; enables PLL-based 120-MHz system clock |
| ETH_MDC, ETH_MDIO | PHY management interface | MII/RMII-compliant MDIO bus for PHY configuration and status monitoring |
| ETH_TXD0–3, ETH_RXD0–3 | Ethernet physical layer I/O | 10/100 Mbps full/half-duplex signaling; requires external PHY or integrated PHY per PMGI |
| USB_DP, USB_DM | USB 2.0 Full-Speed differential pair | On-chip transceiver supports host/function/OTG; no external pull-up required |
| SD_CLK, SD_CMD, SD_DAT0–3 | SD host interface signals | 1-/4-bit SD bus interface compliant with SD Physical Layer Spec v3.01 (no DDR) |
| QSPI_IO0–3, QSPI_CLK, QSPI_CS | Quad SPI interface | Direct connection to quad-output serial flash; supports single/dual/quad I/O modes |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates via background programming and runtime bank switching without halting execution |
| ECC-protected 32-KB RAM | Single-error correction and double-error detection ensures data integrity in safety-critical control tasks |
| Event Link Controller (ELC) | Hardware interconnection of 123 internal events eliminates CPU intervention for timer-triggered ADC sampling or PWM synchronization |
| IEC60730-compliant peripherals | Includes oscillation-stop detection, CRC-A accelerator, IWDTa with window function, and A/D self-diagnostic for Class B certification |
| Integrated graphics subsystem | GLCDC + DRW2D supports 3-plane overlay, 2D vector drawing, bit blitting, and texture rendering - reducing external GPU dependency |
Applications
| Industrial HMI Gateway | Smart Building Controller |
|---|---|
|
Use Scenario: Central controller aggregating Modbus RTU, CANopen, and BACnet MS/TP fieldbus data into Ethernet/IP or MQTT uplinks. IC Role / Device Role / Timing Role: Real-time protocol translation engine with deterministic interrupt latency (<1 µs), synchronized by ELC-linked GPTW and MTU3a timers. Use Value: Dual-bank flash allows over-the-air firmware updates without service interruption; integrated Ethernet MAC + SDHI enables local logging and remote diagnostics. |
Use Scenario: HVAC zone controller managing fan speed, valve position, and occupancy sensing via CAN and analog inputs. IC Role / Device Role / Timing Role: Safety-aware control unit using IEC60730-compliant IWDTa, CRC-A, and A/D self-test to meet UL 60730 Class B requirements. Use Value: On-chip 32-KB ECC RAM protects PID loop variables; temperature sensor enables ambient compensation without external components. |
| Networked PLC Edge Node | Medical Infusion Pump Controller |
|
Use Scenario: Compact programmable logic controller with EtherCAT slave capability and local HMI via parallel LCD interface. IC Role / Device Role / Timing Role: Deterministic real-time executor using RXv3 core with MPU-enforced memory partitioning between control logic and UI stack. Use Value: GLCDC + DRW2D renders dynamic flow diagrams directly from frame buffer; QSPI boots firmware from external serial flash. |
Use Scenario: Battery-powered infusion pump requiring precise motor control, pressure monitoring, and alarm generation. IC Role / Device Role / Timing Role: Low-power safety controller operating in deep software standby mode with RTC wake-up and VBATT-backed real-time dose tracking. Use Value: Four low-power modes + VBATT RTC support >72-hour battery backup; 12-bit D/A drives precision current sources for motor drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566NNDHFB#30 | Same RX66N group, identical 176-pin LQFP (PLQP0176KB-C), but with 2-MB flash and 512-KB SRAM instead of 4-MB/1-MB | Suitable for cost-sensitive designs where firmware size <2 MB and RAM footprint ≤512 KB | Select when full 4-MB flash and 1-MB SRAM are not required; retains same peripheral set and pinout |
| R5F566TNDHFB#30 | Same package and flash/SRAM capacity, but lacks Ethernet MAC, GLCDC, DRW2D, and SDHI; adds extra SCI and CAN channels | Better suited for non-graphical, high-channel-count communication gateways without Ethernet or display needs | Choose when Ethernet, graphics, and SD storage are unnecessary and additional serial/CAN bandwidth is prioritized |
Compared with R5F566NNHDFB#30, R5F566NNDHFB#30 reduces memory resources while maintaining identical I/O and timing capabilities, whereas R5F566TNDHFB#30 trades graphics/Ethernet for expanded serial connectivity - both require no PCB changes but differ in firmware compatibility and feature-enabled use cases.
Availability
R5F566NNHDFB#30 is available at Aetrix Electronics and suitable for industrial HMI, smart building controllers, and networked PLC edge nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-certified designs.
Supply support for R5F566NNHDFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX66N Group - including R5F566NNHDFB#30 - was engineered for high-integration industrial applications demanding real-time performance, functional safety (IEC60730), graphics acceleration, and multi-protocol connectivity in a single chip.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566NNHDFB#30?
The R5F566NNHDFB#30 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under those conditions. This performance stems from the RXv3 CPU core's optimized instruction pipeline, double-precision FPU, and zero-wait-state access to 4-MB flash and 1-MB SRAM - all confirmed in Renesas' R01DS0344EJ0120 datasheet Rev.1.20.
Does the R5F566NNHDFB#30 support IEC60730 Class B compliance out of the box?
Yes, the R5F566NNHDFB#30 includes dedicated hardware features for IEC60730 Class B: oscillation-stoppage detection, CRC-A accelerator, independent watchdog timer (IWDTa) with configurable window function, self-diagnostic A/D converter test, and register write protection. These are documented in Section 1.1 and Table 1.1 of the official datasheet.
What package type and pin count does the R5F566NNHDFB#30 use?
The R5F566NNHDFB#30 uses the PLQP0176KB-C package: a 176-pin LQFP with 24 × 24 mm body size and 0.5-mm lead pitch. It belongs to the D-version temperature grade (–40°C to +85°C) and includes an exposed thermal pad for enhanced thermal dissipation in industrial environments.
Can the R5F566NNHDFB#30 execute firmware updates without interrupting real-time operation?
Yes, the R5F566NNHDFB#30 supports background programming (BGO) and dual-bank flash architecture. This allows one bank to run active firmware while the other is reprogrammed - enabling seamless over-the-air updates. Bank swapping occurs at reset or via software trigger, preserving deterministic timing during critical control cycles.
Which communication interfaces with hardware acceleration are integrated into the R5F566NNHDFB#30?
The R5F566NNHDFB#30 integrates hardware-accelerated interfaces including Ethernet MAC (10/100 Mbps), 3-channel CAN (ISO11898-1), SD host interface (SDHI), QSPI, and a PHY management interface (PMGI). Each has dedicated DMA channels (EDMACa, DMACAa, EXDMAC) and event-linking support to offload CPU overhead during high-throughput transfers.
R5F566NNHDFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX66N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566NNHDFB#30 FAQ
1.How can I place an order for R5F566NNHDFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566NNHDFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566NNHDFB#30 reliable?
The price and inventory of R5F566NNHDFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566NNHDFB#30 is usually 5 days.
3.What payment methods are accepted for R5F566NNHDFB#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566NNHDFB#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F566NNHDFB#30?
R5F566NNHDFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566NNHDFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566NNHDFB#30?
For technical support, including R5F566NNHDFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566NNHDFB#30 requirements.
6.How does Aetrix verify that R5F566NNHDFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F566NNHDFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566NNHDFB#30 meets industry standards.
7.What is the process for return or replacement of R5F566NNHDFB#30?
All R5F566NNHDFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566NNHDFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566NNHDFB#30 part is unused and in its original packaging.
Return procedure for R5F566NNHDFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F566NNHDFB#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

