Renesas R5F566TAAGFN#30
- Part No.:
- R5F566TAAGFN#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
R5F566TAAGFN#30.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 80LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:280
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F566TAAGFN#30 from Renesas is a 32-bit RXv3 microcontroller optimized for motor control and industrial real-time applications, operating at up to 160 MHz with 928 CoreMark performance, 1 MB on-chip code flash, 128 KB SRAM (no wait states), and integrated high-resolution PWM (195 ps minimum resolution) for precise inverter gate timing in servo drives and PMSM/BLDC motor systems.
For engineers reviewing the R5F566TAAGFN#30 datasheet, R5F566TAAGFN#30 pinout, R5F566TAAGFN#30 application, or R5F566TAAGFN#30 equivalent, key selection considerations include its 144-pin LFQFP package with 110 GPIOs (4× 5-V tolerant), dual 12-bit ADC units supporting simultaneous sampling across 30 channels, 32-channel CAN interface compliant with ISO 11898-1, and TSIP-Lite encryption engine supporting AES-128/256 for IEC 60730 Class B safety certification.
Technical Context
The R5F566TAAGFN#30 implements the RXv3 CPU core with single-cycle instruction execution, IEEE 754-compliant single-precision FPU, and configurable endian mode. Its clock system integrates PLL, HOCO (16–20 MHz), LOCO (240 kHz), and main oscillator (8–24 MHz) with independent frequency division for ICLK (up to 160 MHz), PCLKA (120 MHz), PCLKB/C/D (60–160 MHz), enabling concurrent high-speed peripheral operation without CPU bottlenecking.
Real-time control is enabled by tightly coupled peripherals: 10-channel 32-bit GPTW timers with synchronous start/stop and dead-time generation, 9-channel MTU3d for 3-phase complementary PWM, 4-channel HRPWM for sub-nanosecond edge placement, and ELC-driven event chaining that initiates A/D conversion, PWM updates, or DMA transfers without interrupt latency or CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 160 MHz max, 928 CoreMark, IEEE 754 FPU |
| Memory | 1 MB code flash (no wait ≤120 MHz), 128 KB SRAM (no wait), 32 KB data flash (100k erase cycles) |
| Analog Peripherals | 30-channel 12-bit S12ADH ADC with 3 sample-and-hold units; 2× 12-bit D/A; 6-channel CMPC |
| PWM Capability | 10× GPTW (32-bit, 160 MHz), 9× MTU3d (16-bit), 4× HRPWM (195 ps min resolution) |
| Communication | 1× USB 2.0 FS host/function/OTG; 1× CAN (32 mailboxes); 7× SCI; 1× RIIC (400 kbps); 1× RSPI (30 Mbps) |
| Package & I/O | 144-pin LFQFP (20 × 20 mm, 0.5 mm pitch), 110 GPIOs (4× 5-V tolerant, open-drain, pull-up) |
| Safety & Security | IEC 60730 support (oscillation detection, RAM test, CRC, self-diagnostic ADC), TSIP-Lite AES-128/256, MPU, TM |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.5 mm pitch, exposed pad (thermal pad), RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual power domains: VCC (2.7–5.5 V), AVCCx (3.0–5.5 V); separate analog/digital ground pins reduce noise coupling |
| XTAL / EXTAL | Main clock oscillator input/output | Connects to 8–24 MHz crystal/resonator; enables PLL reference for 160 MHz system clock |
| MTIOC0A–MTIOC9B | MTU3d timer I/O | 9-channel multifunction timer pins supporting PWM output, input capture, phase counting, and dead-time compensation |
| GTIOCA0–GTIOCB3 | GPTW waveform I/O | 10-channel general PWM timer outputs with complementary pairs; supports single-/3-/5-phase PWM modes |
| ADTRG0–ADTRG2 | A/D conversion trigger inputs | Hardware-triggered sampling from MTU3/GPTW/ELC events ensures deterministic timing for motor current sensing |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 full-speed interface | Integrated transceiver supports host/function/OTG; no external resistors required; VBUS detection enables bus-powered mode |
| CAN_TX / CAN_RX | CAN bus interface | Differential signaling compliant with ISO 11898-1; 32 dedicated mailboxes enable prioritized message handling in multi-node networks |
| SCI11_TXD / SCI11_RXD | High-speed serial interface | FIFO-buffered (16-byte TX/RX) SCI channel for low-latency UART communication with minimal CPU overhead |
Key Features
| Feature | Design Value |
|---|---|
| Event Link Controller (ELC) | 188 internal event signals routed without CPU involvement-enables hardware-synchronized PWM update + ADC sampling + DMA transfer in <1 µs |
| Simultaneous Sampling ADC | Three independent 12-bit S12ADH units (30 total channels) with synchronized start triggers for accurate three-phase current reconstruction |
| High-Resolution PWM Timing | HRPWM overlays 195 ps fine-tuning on GPTW outputs-critical for minimizing dead-time uncertainty in SiC/GaN inverter gate drivers |
| Trusted Secure IP Lite (TSIP-Lite) | AES-128/256 encryption, true random number generator, and secure key management-meets IEC 60730 Annex H requirements for Class B safety |
| Motor Control Optimized Timers | GPTW + MTU3d + POE3B + HRPWM form an integrated motor control subsystem-supports field-oriented control (FOC) with hardware-accelerated space vector modulation |
Applications
| Industrial Servo Drives | Automotive EPS (Electric Power Steering) |
|---|---|
Use Scenario: Real-time closed-loop control of PMSM motors in CNC machine tools requiring <1 µs current loop update and harmonic distortion <2% THD. IC Role / Device Role / Timing Role: Primary motor control MCU executing FOC algorithm, managing 3-phase PWM generation, sampling dual shunt currents via simultaneous ADC, and communicating via CAN to higher-level motion controller. Use Value: Integrated 195 ps HRPWM and ELC-synchronized ADC eliminate software jitter-enabling >20 kHz switching frequencies with stable torque ripple under dynamic load. | Use Scenario: Compact, ASIL-B-compliant steering assist unit where thermal margin, functional safety, and electromagnetic robustness are critical. IC Role / Device Role / Timing Role: Safety-certified MCU performing torque calculation, motor phase commutation, fault monitoring (overcurrent, overtemperature, CAN timeout), and secure firmware update via encrypted USB/SCI. Use Value: TSIP-Lite AES + CAC clock accuracy measurement + oscillation stop detection satisfy ISO 26262 diagnostic coverage requirements without external safety co-processor. |
| Home Appliance Inverter Compressors | Renewable Energy Solar Inverters |
Use Scenario: Variable-speed compressor control in HVAC systems demanding high efficiency (>95%), low acoustic noise, and rapid load response. IC Role / Device Role / Timing Role: Main inverter controller managing DC-link voltage regulation, sinusoidal PWM generation, refrigerant pressure feedback, and user interface via SCI/USB. Use Value: 128 KB zero-wait SRAM hosts real-time FOC and sensorless estimation algorithms; 32 KB data flash stores adaptive PID tuning parameters across power cycles. | Use Scenario: Grid-tied solar microinverter with MPPT tracking, anti-islanding detection, and reactive power support per IEEE 1547. IC Role / Device Role / Timing Role: Dual-role controller executing MPPT algorithm, grid synchronization (PLL), PWM modulation, and communication with smart meter via CAN/RS485. Use Value: Simultaneous 30-channel ADC sampling captures DC input voltage/current and AC line voltage/current with <1 µs skew-essential for precise harmonic analysis and grid compliance testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor control MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TAADFN#30 | Same RX66T Group silicon, but 512 KB code flash (vs. 1 MB), 64 KB SRAM (vs. 128 KB), identical 144-pin LFQFP package and peripheral set | Targeted at cost-sensitive servo drives with smaller firmware footprint and reduced current-sensing channel count | Select when application firmware size <400 KB and simultaneous ADC channel requirement ≤16 |
| R5F566TADDFN#30 | Same 1 MB flash/128 KB SRAM configuration, but 100-pin LFQFP (PLQP0100KB-B), 69 GPIOs, no USB interface, retains CAN/SCI/ADC/PWM | Suitable for space-constrained industrial PLC I/O modules where USB debug is unnecessary and board area is premium | Select when USB functionality is unused and PCB real estate limits package size to ≤14 × 14 mm |
Compared with R5F566TAAGFN#30, the R5F566TAADFN#30 reduces memory capacity while maintaining identical real-time control features-ideal for scaled-down implementations-whereas the R5F566TADDFN#30 trades package size and USB for compact deployment in embedded nodes where CAN and deterministic PWM remain essential.
Availability
R5F566TAAGFN#30 is available at Aetrix Electronics and suitable for industrial servo drives, automotive EPS systems, HVAC inverter compressors, and solar microinverters requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical designs.
Supply support for R5F566TAAGFN#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.
The RX66T Group is a 32-bit MCUs product line purpose-built for high-performance motor control, featuring integrated high-resolution PWM, simultaneous sampling ADC, and functional safety features targeting IEC 60730 and ISO 26262 compliance.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566TAAGFN#30?
The R5F566TAAGFN#30 operates at a maximum frequency of 160 MHz and achieves 928 CoreMark performance. This benchmark reflects its RXv3 CPU core's efficient pipeline, single-cycle instruction execution, and integrated FPU-enabling complex motor control algorithms such as field-oriented control (FOC) and model predictive control (MPC) to execute within strict real-time deadlines. The R5F566TAAGFN#30 sustains this performance across its full temperature range (–40°C to +85°C).
Does the R5F566TAAGFN#30 support simultaneous sampling across all 30 ADC channels?
No-the R5F566TAAGFN#30 supports simultaneous sampling only across groups of channels within its three independent S12ADH units: Unit 0 (8 channels, 3 sample-and-hold circuits), Unit 1 (8 channels, 3 sample-and-hold circuits), and Unit 2 (14 channels, no sample-and-hold). True simultaneous sampling is limited to up to 7 channels per unit when using the sample-and-hold function. Unit 2 provides 14 channels but lacks sample-and-hold, so conversions occur sequentially unless triggered by synchronized ELC events.
What safety certifications and features does the R5F566TAAGFN#30 provide for IEC 60730 compliance?
The R5F566TAAGFN#30 includes dedicated hardware features for IEC 60730 Class B compliance: oscillation-stoppage detection, A/D converter disconnection detection, clock frequency accuracy measurement circuit (CAC), independent watchdog timer (IWDT) with window function, RAM test-assisting function via DOC, CRC calculator (CRCA), and register write protection. These are implemented in silicon-not software libraries-ensuring deterministic behavior and eliminating reliance on external components for safety-critical diagnostics.
Can the R5F566TAAGFN#30 operate with a 5-V supply, and what I/O pins are 5-V tolerant?
Yes-the R5F566TAAGFN#30 operates from a single 2.7–5.5 V supply and features four 5-V tolerant I/O pins (confirmed in the 144-pin LFQFP variant). These pins tolerate 5 V even when VCC is at minimum 2.7 V, enabling direct interfacing with legacy 5-V logic, sensors, or level-shifting-free communication with industrial fieldbus transceivers. All other GPIOs are 3.3-V compatible and must not exceed AVCC levels.
What is the resolution and minimum step size of the HRPWM in the R5F566TAAGFN#30?
The High-Resolution PWM (HRPWM) in the R5F566TAAGFN#30 provides a minimum resolution of 195 ps when operating at 160 MHz. This corresponds to one LSB of timing adjustment on the underlying 32-bit GPTW timer outputs-enabling precise dead-time insertion, phase advance correction, and gate drive skew compensation essential for SiC and GaN-based inverter designs where nanosecond-level timing control directly impacts efficiency and EMI performance.
R5F566TAAGFN#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 80-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 19x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566TAAGFN#30 FAQ
1.How can I place an order for R5F566TAAGFN#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566TAAGFN#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566TAAGFN#30 reliable?
The price and inventory of R5F566TAAGFN#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566TAAGFN#30 is usually 5 days.
3.What payment methods are accepted for R5F566TAAGFN#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566TAAGFN#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F566TAAGFN#30?
R5F566TAAGFN#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566TAAGFN#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566TAAGFN#30?
For technical support, including R5F566TAAGFN#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566TAAGFN#30 requirements.
6.How does Aetrix verify that R5F566TAAGFN#30 is sourced from the original manufacturer or authorized distributors?
All R5F566TAAGFN#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566TAAGFN#30 meets industry standards.
7.What is the process for return or replacement of R5F566TAAGFN#30?
All R5F566TAAGFN#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566TAAGFN#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566TAAGFN#30 part is unused and in its original packaging.
Return procedure for R5F566TAAGFN#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F566TAAGFN#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

