Renesas R5F566TAEGFH#10
- Part No.:
- R5F566TAEGFH#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 112-LQFP
- Datasheet:
-
R5F566TAEGFH#10.pdf
- Description:
- IC MCU 32BIT 256KB FLSH 112LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F566TAEGFH#10 from Renesas is a 32-bit RXv3 core microcontroller operating at up to 160 MHz, featuring 1 MB code flash, 128 KB SRAM, 32 KB data flash with 100,000 write cycles, and integrated 12-bit A/D (30-channel), 12-bit D/A (2-channel), 6-channel analog comparator, and high-resolution PWM (195 ps min resolution). It targets industrial motor control systems requiring precise timing, safety compliance (IEC60730), and real-time PWM waveform generation.
For engineers reviewing the R5F566TAEGFH#10 datasheet, R5F566TAEGFH#10 pinout, R5F566TAEGFH#10 application, or R5F566TAEGFH#10 equivalent, key selection criteria include its 144-pin LFQFP package, 160 MHz GPTW/MTU3 timer operation, USB 2.0 FS host/function capability, CAN 2.0B support, and TSIP-Lite encryption for secure firmware updates in embedded motor drives.
Technical Context
The R5F566TAEGFH#10 implements the RXv3 CPU core with single-cycle instruction execution, IEEE 754-compliant FPU, and configurable endian mode. Its clock system integrates PLL, HOCO (16–20 MHz), LOCO (240 kHz), and main oscillator (8–24 MHz) with independent PCLKA/PCLKB/PCLKC/PCLKD domains enabling concurrent peripheral operation at different frequencies - e.g., GPTW at 160 MHz (PCLKC), S12ADH at 60 MHz (ADCLK), and USB at 48 MHz.
Real-time control is enabled by ELC-driven event linking between 188 internal signals, eliminating CPU intervention for timer-triggered ADC sampling, PWM dead-time compensation, and comparator-based fault shutdown. Safety features include oscillation-stop detection, CAC clock accuracy monitoring, CRCA CRC calculation, register write protection, and Trusted Memory protecting flash blocks 8–9.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 160 MHz max, 928 CoreMark, IEEE 754 FPU |
| Memory | 1 MB code flash (no wait ≤120 MHz), 128 KB SRAM (no wait), 32 KB data flash (100k erase/write) |
| Analog Peripherals | 30-channel 12-bit S12ADH ADC (3 sample-and-hold units), 2-channel 12-bit R12DAb DAC, 6-channel CMPC comparator |
| PWM System | 10-channel 32-bit GPTW + 9-channel 16-bit MTU3d + 4-channel HRPWM (195 ps resolution @160 MHz) |
| Communication | USB 2.0 FS host/function (1 port), CAN 2.0B (32 mailboxes), RIICa (400 kbps), RSPIc (30 Mbps), 7× SCI |
| Security & Safety | TSIP-Lite AES-128/256, CRCA, CAC, MPU, Trusted Memory, IEC60730 self-test functions |
| Package & Environment | 144-pin LFQFP (20 × 20 mm, 0.5 mm pitch), –40°C to +105°C (G-version) |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.5 mm pitch, exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Core logic (2.7–5.5 V), analog (3.0–5.5 V), USB (3.0–3.6 V) domains with separate pins |
| XTAL, EXTAL | Main clock oscillator interface | Connects external 8–24 MHz crystal/resonator for PLL reference; supports oscillation-stop detection |
| USB_DP, USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver; no external pull-ups required; supports host/function/OTG modes |
| TXA0–TXA6, RXA0–RXA6 | SCI serial communication lines | 7 independent SCI channels supporting UART, SPI, I²C, LIN, smart-card, and clock-synchronous modes |
| CTX0–CTX3, CRX0–CRX3 | CAN bus interface | Single CAN 2.0B channel with 32 mailboxes; supports standard/extended frames and loopback self-test |
| GTIOA0–GTIOA9, GTIOB0–GTIOB9 | GPTW PWM output pins | 10-channel complementary PWM outputs with programmable dead time, phase counting, and ELC-triggered fault shutdown |
| AD00–AD29 | Analog input channels | 30 dedicated ADC inputs across three units; includes PGA pseudo-differential inputs on select pins |
| DA00, DA01 | Digital-to-analog outputs | 2-channel 12-bit DAC; outputs usable as comparator reference voltage sources |
Key Features
| Feature | Design Value |
|---|---|
| High-resolution PWM timing | HRPWM achieves 195 ps minimum edge placement resolution synchronized to GPTW0–GPTW3, enabling sub-nanosecond dead-time control in 3-phase inverter gate drivers |
| Event Link Controller (ELC) | 188 internal event signals routed without CPU involvement - e.g., MTU3 overflow triggers ADC conversion, comparator output disables PWM via POE3B, reducing interrupt latency to <100 ns |
| IEC60730 Class B compliance support | Integrated hardware diagnostics: oscillation-stop detection, RAM test assist (DOC), CRC calculator (CRCA), clock accuracy measurement (CAC), and register write protection for fail-safe motor control |
| Secure firmware execution | Trusted Secure IP Lite (TSIP-Lite) provides AES-128/256 encryption, true random number generation, and key management - blocks 8–9 of flash protected by Trusted Memory to prevent unauthorized readout |
| Flexible power domain control | Four low-power modes (Sleep, All-module clock stop, Software standby, Deep software standby) with selective peripheral clock gating and wake-up via ELC-linked events or IRQ pins |
Applications
| Industrial Motor Drives | Robotics Actuation Systems |
|---|---|
Use Scenario: Closed-loop field-oriented control (FOC) of 3-phase PMSM/BLDC motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Primary motion controller executing FOC algorithm, generating synchronized 3-phase complementary PWM with nanosecond-level dead-time precision via GPTW+HRPWM, and sampling current/voltage via simultaneous 3-unit ADC. Use Value: Enables <1 µs current-loop update rates and <±0.5% torque ripple through deterministic 160 MHz timer operation and ELC-triggered ADC sampling without CPU overhead. | Use Scenario: Multi-axis servo drive in collaborative robots requiring functional safety and secure firmware updates. IC Role / Device Role / Timing Role: Real-time motion controller with integrated CAN for distributed axis coordination, USB for configuration, and TSIP-Lite for encrypted firmware validation during OTA updates. Use Value: Meets IEC61800-5-2 requirements via hardware CRC, CAC, and memory protection - eliminates need for external safety monitors while maintaining 100 kHz PWM switching. |
| Renewable Energy Inverters | Electric Vehicle Onboard Chargers |
Use Scenario: Grid-tied solar microinverters requiring high-efficiency MPPT and anti-islanding detection. IC Role / Device Role / Timing Role: System controller managing DC-DC boost stage and H-bridge inverter using dual GPTW units for interleaved PWM, with 12-bit DAC providing reference for analog comparators in zero-voltage switching detection. Use Value: Simultaneous sampling across 30 ADC channels enables real-time grid voltage/current harmonics analysis and fast anti-islanding response (<20 ms) per UL1741. | Use Scenario: Bidirectional AC/DC conversion in EV onboard chargers with CAN communication to vehicle battery management system. IC Role / Device Role / Timing Role: Main controller handling power factor correction (PFC), DC-DC isolation, and CAN FD messaging (via external transceiver), leveraging 160 MHz timers for adaptive frequency modulation of resonant LLC converters. Use Value: Integrated 32 KB data flash supports secure logging of charge cycle data; TSIP-Lite ensures cryptographic integrity of charging session keys exchanged over CAN. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor control MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEAGFH#10 | Same RX66T Group, identical 144-pin LFQFP package and 1 MB flash, but with 64 KB SRAM (vs. 128 KB) and no PGA pseudo-differential amplifier channels | Suitable for cost-sensitive motor control where simultaneous multi-channel analog sensing is not required | Select when system memory footprint fits within 64 KB SRAM and PGA functionality is unused |
| R5F566TBEGFH#10 | Same package and memory size, but rated for –40°C to +85°C (D-version) instead of –40°C to +105°C (G-version); lacks Trusted Memory protection for flash blocks 8–9 | Applicable in commercial-grade industrial equipment without extended temperature or security certification needs | Choose for non-safety-critical applications operating below 85°C ambient with reduced security requirements |
Compared with R5F566TAEGFH#10, the R5F566TEAGFH#10 reduces SRAM and removes PGA capability for lower BOM cost, while the R5F566TBEGFH#10 trades extended temperature rating and flash security for broader commercial availability - neither offers pin-compatible replacement without firmware and layout review due to functional subset differences.
Availability
R5F566TAEGFH#10 is available at Aetrix Electronics and suitable for industrial motor drives, robotics actuation systems, renewable energy inverters, and electric vehicle onboard chargers requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for R5F566TAEGFH#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor manufacturer headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and IoT markets.
The RX66T Group is designed specifically for high-performance real-time motor control applications, integrating advanced PWM timing, safety-certified peripherals, and secure execution environments to replace discrete analog/motor control ICs with a single-chip solution.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566TAEGFH#10?
The R5F566TAEGFH#10 operates at a maximum frequency of 160 MHz and achieves 928 CoreMark points under benchmark conditions. This performance stems from the RXv3 CPU core's single-cycle instruction execution, 32-bit multiplier/divider, barrel shifter, and optional ROM cache - all validated in the official Renesas R01DS0315EJ0130 datasheet Rev.1.30. The R5F566TAEGFH#10 sustains this speed across its 1 MB flash and 128 KB SRAM with zero wait states up to 120 MHz.
Does the R5F566TAEGFH#10 support IEC60730 Class B compliance out of the box?
Yes, the R5F566TAEGFH#10 includes hardware features required for IEC60730 Class B compliance: oscillation-stop detection, clock frequency accuracy measurement (CAC), CRC calculator (CRCA), RAM test-assist function (DOC), independent watchdog timer (IWDT), and register write protection. These are implemented in silicon and documented in the R01DS0315EJ0130 datasheet. The R5F566TAEGFH#10 also provides software libraries and application notes from Renesas to streamline certification - no external components are needed to meet core diagnostic requirements.
What PWM resolution and channel count does the R5F566TAEGFH#10 provide for motor control?
The R5F566TAEGFH#10 delivers 10 channels of 32-bit GPTW PWM, 9 channels of 16-bit MTU3d PWM, and 4 dedicated HRPWM channels achieving a minimum edge placement resolution of 195 ps at 160 MHz. This enables precise dead-time control in 3-phase inverters and supports single-phase, 3-phase, and 5-phase complementary PWM modes. All PWM units synchronize via the Event Link Controller (ELC), allowing deterministic triggering of ADC sampling and fault shutdown - critical for high-fidelity motor control in the R5F566TAEGFH#10.
Can the R5F566TAEGFH#10 interface directly with USB and CAN without external transceivers?
The R5F566TAEGFH#10 integrates a full-speed USB 2.0 transceiver (USBb module) and requires no external components for USB connectivity - including internal pull-ups and voltage regulation support. For CAN, it contains a protocol controller compliant with ISO11898-1 but requires an external CAN physical-layer transceiver (e.g., TJA1042) on the CTX0/CRX0 pins. The R5F566TAEGFH#10's CAN module supports 32 mailboxes, standard/extended frames, and loopback self-test - all confirmed in the R01DS0315EJ0130 datasheet.
What is the analog peripheral configuration of the R5F566TAEGFH#10?
The R5F566TAEGFH#10 integrates a 30-channel 12-bit A/D converter (S12ADH) organized into three units (8+8+14 channels), two 12-bit D/A converters (R12DAb), and six analog comparators (CMPC). Units 0 and 1 each include three programmable gain amplifier (PGA) channels supporting pseudo-differential input, while unit 2 provides 14 single-ended channels. The R5F566TAEGFH#10 supports simultaneous sampling across all three units and uses the DAC outputs as comparator references - capabilities verified in the R01DS0315EJ0130 datasheet Section 1.1.
R5F566TAEGFH#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 112-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 84
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 22x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566TAEGFH#10 FAQ
1.How can I place an order for R5F566TAEGFH#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566TAEGFH#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of R5F566TAEGFH#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566TAEGFH#10 is usually 5 days.
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For technical support, including R5F566TAEGFH#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566TAEGFH#10 requirements.
6.How does Aetrix verify that R5F566TAEGFH#10 is sourced from the original manufacturer or authorized distributors?
All R5F566TAEGFH#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566TAEGFH#10 meets industry standards.
7.What is the process for return or replacement of R5F566TAEGFH#10?
All R5F566TAEGFH#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566TAEGFH#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566TAEGFH#10 part is unused and in its original packaging.
Return procedure for R5F566TAEGFH#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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