Renesas R5F566TEADFN#10
- Part No.:
- R5F566TEADFN#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
R5F566TEADFN#10.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 80LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:906
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Product details
Overview
R5F566TEADFN#10 from Renesas is a 120 MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 2 MB on-chip code flash, 1 MB SRAM (512 KB + 512 KB expansion), and integrated Ethernet MAC, CAN, USB 2.0 FS, SDHI, and QSPI - designed for industrial HMI, gateway, and edge node applications requiring real-time control and connectivity.
For engineers reviewing the R5F566TEADFN#10 datasheet, R5F566TEADFN#10 pinout, R5F566TEADFN#10 application, or R5F566TEADFN#10 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-B (144-pin LQFP, 20 × 20 mm, 0.5 mm pitch), functional role in networked embedded systems, and validated alternative options for migration or sourcing continuity.
Technical Context
The R5F566TEADFN#10 implements the RXv3 CPU core with 698 CoreMark at 120 MHz, supporting little-endian data and instruction execution in single-cycle states. It integrates dual-bank flash enabling background programming and bank-swapping during operation, alongside ECC-protected 32 KB RAM and 8 KB standby RAM backed by VBATT.
Its peripheral set includes an Ethernet MAC (10/100 Mbps, MII/RMII), three CAN channels (ISO 11898-1 compliant, 32 mailboxes each), and a full-featured graphics subsystem (GLCDC + DRW2D) - all synchronized to independent clock domains (PCLKA up to 120 MHz, PCLKB up to 60 MHz) managed by a multi-PLL clock generator.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision FPU (IEEE-754) |
| Memory | 2 MB code flash (dual-bank, BGO support), 1 MB SRAM (512 KB + 512 KB), 32 KB ECC RAM, 8 KB standby RAM |
| Connectivity | Ethernet MAC (10/100 Mbps), 3× CAN (ISO 11898-1), USB 2.0 FS host/function/OTG, SDHI (25 MB/s), QSPI, 3× I²C (up to 1 Mbps) |
| Analog | Two 12-bit A/D units (8 + 21 channels), 2× 12-bit D/A, on-chip temperature sensor |
| Timers & PWM | 4× GPTW (32-bit), 9× MTU3a (16/32-bit), 6× TPUa (16-bit), 4× TMR (8-bit), CMT/CMTW, RTC with battery backup |
| Package | PLQP0144KA-B: 144-pin LQFP, 20 × 20 mm, 0.5 mm pitch, –40°C to +85°C (D-version) |
| Security | Optional TSIP (Trusted Secure IP) and AES-128/192/256 encryption engines |
Pinout & Package
Package: PLQP0144KA-B - 144-pin LQFP, 20 × 20 mm body, 0.5 mm pitch, exposed pad, RoHS-compliant, rated for –40°C to +85°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog domain supplies (2.7–3.6 V); AVCC0/AVCC1 power ADC, DAC, and analog comparators |
| VSS, AVSS | Ground references | Digital/analog ground separation supports noise-sensitive analog performance and signal integrity |
| XTAL, EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal for precise system clock generation and PLL reference |
| RES#, NMI | Reset and non-maskable interrupt | Active-low hardware reset; NMI enables high-priority fault or watchdog escalation handling |
| ETH_MDC, ETH_MDIO, ETH_TXD[3:0], ETH_RXD[3:0] | Ethernet PHY interface | MII-compliant 4-bit transmit/receive data bus with management clock/data for external PHY connection |
| USB_VBUS, USB_D+, USB_D− | USB 2.0 Full-Speed transceiver | On-chip transceiver supports host/device/OTG; VBUS sensing enables dynamic role switching |
| SD0_CLK, SD0_CMD, SD0_DAT[3:0] | SD host interface signals | 4-bit SD bus interface supporting SD memory and SDIO cards up to 25 MB/s (high-speed mode) |
| QSPI_IO0–QSPI_IO3, QSPI_CLK, QSPI_CS | Quad SPI interface | Direct connection to quad-output serial flash; supports single/dual/quad I/O modes with configurable clock phase/polarity |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates via background programming and startup bank swapping without system interruption |
| Ethernet + CAN + USB coexistence | Hardware-accelerated concurrent protocol stacks reduce CPU load in industrial gateways and multi-protocol edge devices |
| GLCDC + DRW2D graphics engine | Offloads GUI rendering from CPU: supports 3-plane overlay, 32-bit pixel formats, and vector/bit-blit operations for HMI displays |
| Event Link Controller (ELC) | Hardware interconnect for 123 internal events eliminates software polling and ISR overhead for timer-triggered ADC or PWM actions |
| IEC 60730 safety support | Includes oscillation-stop detection, CRC accelerators, IWDT windowing, register write protection, and ADC self-diagnostic functions |
Applications
| Industrial Gateway | Smart HMI Terminal |
|---|---|
|
Use Scenario: Aggregating Modbus RTU, CANopen, and EtherNet/IP fieldbus data into MQTT/HTTP payloads for cloud upload. IC Role / Device Role / Timing Role: Central protocol translator and real-time scheduler with deterministic Ethernet and CAN timing. Use Value: Dual-bank flash allows over-the-air firmware updates while maintaining fieldbus uptime; 120 MHz CPU handles multiple concurrent protocol stacks. |
Use Scenario: Driving 480×272 TFT LCD with animated UI, touch input, and local data logging via SD card. IC Role / Device Role / Timing Role: Graphics controller and display processor with GLCDC/DRW2D offloading rendering tasks from main application logic. Use Value: Integrated 2D drawing engine reduces frame buffer bandwidth; SDHI supports 25 MB/s writes for video capture or log buffering. |
| Edge IoT Node | Networked Power Monitor |
|
Use Scenario: Monitoring energy consumption across three-phase AC circuits with isolation, wireless telemetry, and local analytics. IC Role / Device Role / Timing Role: Real-time sensor fusion hub with synchronized 12-bit ADC sampling, CAN-based sensor bus, and encrypted TLS stack. Use Value: On-chip AES and TSIP enable secure key storage and authenticated firmware; 32 KB ECC RAM protects critical runtime variables. |
Use Scenario: DIN-rail mounted meter collecting voltage/current harmonics, thermal data, and event logs for predictive maintenance. IC Role / Device Role / Timing Role: Precision measurement controller with RTC timestamping, 12-bit dual A/D units, and Ethernet-based alarm reporting. Use Value: Independent RTC with battery backup ensures accurate time-stamping during brownouts; 21-channel A/D unit supports multi-sensor analog front-end. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFP#30 | Same RX66N core, identical peripherals and memory, but in PLQP0176KB-C (176-pin LQFP, 24 × 24 mm) | Requires PCB layout change due to larger footprint and additional I/O pins (182 vs. 136) | Select when higher pin count is needed for expanded I/O, additional CAN/Ethernet PHY routing, or future-proofing. |
| R5F566TAADFN#10 | Same package (PLQP0144KA-B), same core, but reduced memory: 1 MB flash, 512 KB SRAM, no Ethernet MAC or GLCDC | Suitable for cost-sensitive control-only applications without networking or graphics requirements | Choose for simpler automation controllers where Ethernet, SDHI, and DRW2D are unnecessary - lower BOM cost and power. |
Compared with R5F566TEADFN#10, R5F566TEADFP#30 offers more I/O and routing flexibility at the expense of board space, while R5F566TAADFN#10 sacrifices connectivity and graphics capability for cost reduction - both require design validation for pin compatibility and peripheral enablement.
Availability
R5F566TEADFN#10 is available at Aetrix Electronics and suitable for industrial gateways, smart HMI terminals, edge IoT nodes, networked power monitors, and IEC 60730-certified equipment requiring stable component supply and long-term lifecycle assurance.
Supply support for R5F566TEADFN#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX66N Group - including R5F566TEADFN#10 - was designed for high-performance, safety-aware industrial edge devices requiring integrated networking, graphics, and real-time determinism in compact form factors.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566TEADFN#10?
The R5F566TEADFN#10 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under benchmark conditions. This performance stems from its RXv3 CPU core with optimized pipeline, double-precision FPU, and zero-wait-state access to 2 MB flash and 1 MB SRAM - enabling deterministic real-time execution in demanding industrial applications.
Does the R5F566TEADFN#10 include hardware acceleration for graphics or cryptography?
Yes, the R5F566TEADFN#10 integrates both a Graphic-LCD Controller (GLCDC) and a 2D Drawing Engine (DRW2D) for hardware-accelerated UI rendering, plus optional Trusted Secure IP (TSIP) and AES-128/192/256 engines for cryptographic operations. These features are confirmed in the R01DS0344EJ0120 datasheet and enable secure, responsive HMI and edge-node implementations without external co-processors.
What package type and dimensions does the R5F566TEADFN#10 use?
The R5F566TEADFN#10 uses the PLQP0144KA-B package: a 144-pin LQFP with 20 × 20 mm body size, 0.5 mm pin pitch, and exposed thermal pad. It is rated for industrial temperature range (–40°C to +85°C) and complies with RoHS directives - matching the mechanical and thermal specifications defined in Renesas' official packaging documentation.
Which communication interfaces are supported by the R5F566TEADFN#10?
The R5F566TEADFN#10 supports Ethernet MAC (10/100 Mbps, MII/RMII), three ISO 11898-1 CAN channels (32 mailboxes each), USB 2.0 Full-Speed host/function/OTG, SD host interface (25 MB/s), quad SPI, three I²C buses (up to 1 Mbps), 13 SCI channels, and RSPI - all documented in the R01DS0344EJ0120 datasheet's peripheral overview and function tables.
Is the R5F566TEADFN#10 suitable for IEC 60730 safety-critical applications?
Yes, the R5F566TEADFN#10 includes dedicated IEC 60730 compliance features: oscillation-stop detection, hardware CRC accelerators, windowed independent watchdog timer (IWDTa), register write protection, and self-diagnostic functions for the A/D converter - all explicitly listed in the "Useful functions for IEC60730 compliance" section of the R01DS0344EJ0120 datasheet.
R5F566TEADFN#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 80-LQFP
- Series:
- RX66T
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 19x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566TEADFN#10 FAQ
1.How can I place an order for R5F566TEADFN#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566TEADFN#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566TEADFN#10 reliable?
The price and inventory of R5F566TEADFN#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566TEADFN#10 is usually 5 days.
3.What payment methods are accepted for R5F566TEADFN#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566TEADFN#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F566TEADFN#10?
R5F566TEADFN#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566TEADFN#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566TEADFN#10?
For technical support, including R5F566TEADFN#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566TEADFN#10 requirements.
6.How does Aetrix verify that R5F566TEADFN#10 is sourced from the original manufacturer or authorized distributors?
All R5F566TEADFN#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566TEADFN#10 meets industry standards.
7.What is the process for return or replacement of R5F566TEADFN#10?
All R5F566TEADFN#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566TEADFN#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566TEADFN#10 part is unused and in its original packaging.
Return procedure for R5F566TEADFN#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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