Renesas R5F566TEADFP#10
- Part No.:
- R5F566TEADFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F566TEADFP#10.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:720
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Product details
Overview
R5F566TEADFP#10 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 2 MB on-chip code flash, 1 MB SRAM (512 KB + 512 KB expansion), and integrated Ethernet MAC, CAN, SDHI, QSPI, and GLCDC. It targets industrial HMI, networked gateway, and real-time control applications requiring deterministic timing, secure boot, and rich peripheral integration.
For engineers reviewing the R5F566TEADFP#10 datasheet, R5F566TEADFP#10 pinout, R5F566TEADFP#10 application, or R5F566TEADFP#10 equivalent, this page delivers verified specifications, package mapping to PLQP0176KB-C (176-pin LQFP), validated pin functions, real-world use cases in industrial gateways and HMI systems, and two confirmed alternative MCUs with documented functional and packaging differences.
Technical Context
The R5F566TEADFP#10 implements the RXv3 CPU core with 698 CoreMark at 120 MHz, supporting little-endian data and single/double-precision IEEE-754 floating-point arithmetic. Its memory subsystem includes dual-bank 2 MB flash enabling background programming and bank-swapping, plus 1 MB SRAM split into 512 KB no-wait RAM, 32 KB ECC RAM (SEC-DED), and 8 KB standby RAM backed by VBATT.
Peripherals are clocked across four domains: ICLK (up to 120 MHz for CPU), PCLKA (up to 120 MHz for ETHERC, GLCDC, DRW2D), PCLKB (up to 60 MHz for TPU, MTU3, SCI), and PCLKC/PCLKD (up to 60 MHz for S12AD units). The device integrates three CAN channels (ISO 11898-1 compliant, 32 mailboxes each), one 10/100 Mbps Ethernet MAC with MII/RMII, and a full-featured SD host interface supporting 25 MB/s high-speed mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision FPU, 16×32-bit GPRs, MPU support |
| Memory | 2 MB code flash (dual-bank, BGO), 32 KB data flash (100k erase cycles), 1 MB SRAM (512 KB + 512 KB expansion) |
| Package & Pins | PLQP0176KB-C 176-pin LQFP (24 × 24 mm, 0.5 mm pitch), 136 general-purpose I/O pins, 19× 5-V tolerant |
| Connectivity | Ethernet MAC (10/100 Mbps, MII/RMII), 3× CAN (ISO 11898-1), SDHI (25 MB/s), QSPI, 13× SCI, 3× RIIC, USB 2.0 FS OTG |
| Analog | Two 12-bit ADC units (8 + 21 channels), 2× 12-bit DAC, on-chip temperature sensor, self-diagnostic ADC |
| Timers & PWM | 4× GPTW (32-bit), 6× TPUa (16-bit), 9× MTU3a (16/32-bit), 4× TMRa (8-bit), CMT/CMTW, RTC with battery backup |
| Security & Compliance | Optional TSIP encryption engine (AES-128/192/256), IEC 60730 Class B support (CRC, IWDTa, oscillator detection, A/D self-test) |
Pinout & Package
Package: PLQP0176KB-C - 176-pin Low-profile Quad Flat Package (24 × 24 mm, 0.5 mm pitch), RoHS-compliant, lead-free, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog supply (2.7–3.6 V); separate AVCC domains enable noise-isolated analog operation |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/timekeeping in deep software standby |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; required for precise Ethernet/USB timing and RTC accuracy |
| MD0–MD2 | Mode setting pins | Determine boot source (SCI/USB/FINE) and operating mode at reset release; fixed pull-up/pull-down required |
| ETH_MDC / ETH_MDIO | PHY management interface | IEEE 802.3u-compliant MDIO bus for PHY register access; offloads PHY configuration from CPU |
| ETXD0–ETXD3 / ERXD0–ERXD3 | Ethernet MAC data lines | MII interface signals; support 10/100 Mbps full/half-duplex; require controlled impedance routing |
| CRX0 / CTX0 | CAN channel 0 differential pair | ISO 11898-1 compliant physical layer interface; requires external CAN transceiver and termination |
| SD0DAT0–SD0DAT3 | SD host 4-bit data bus | Direct connection to SD memory cards; supports high-speed mode (25 MB/s) and SDIO peripherals |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates via background programming and bank-swapping without halting execution |
| Integrated Ethernet MAC + PMGI | Reduces external component count; PMGI hardware offloads PHY register reads/writes from CPU |
| GLCDC + DRW2D graphics engine | Drives up to WXGA LCD panels directly; 2D engine accelerates UI rendering (bitblit, rotation, vector draw) |
| IEC 60730 Class B compliance suite | Includes hardware CRC, IWDTa with windowing, oscillator stop detection, and A/D self-test for safety-critical firmware |
| Event Link Controller (ELC) | Hardware interconnect for 123 internal events; eliminates CPU polling and ISR overhead for timer-triggered ADC captures |
| TSIP optional security module | On-chip AES acceleration and key management; supports secure boot, firmware authentication, and encrypted storage |
Applications
| Industrial Gateway | HMI Controller |
|---|---|
Use Scenario: Edge gateway aggregating Modbus RTU, CANopen, and EtherNet/IP fieldbus data for cloud upload via TLS-secured Ethernet. IC Role / Device Role / Timing Role: Central protocol translator and real-time scheduler; Ethernet MAC handles TCP/IP stack while MTU3 timers manage deterministic fieldbus frame timing. Use Value: Dual-bank flash enables zero-downtime firmware updates over-the-air; integrated CAN/Ethernet reduces BOM cost and PCB area vs. discrete PHY + MCU solutions. |
Use Scenario: Touch-enabled operator panel with 7-inch TFT display, local data logging, and alarm management in factory automation. IC Role / Device Role / Timing Role: Graphics controller and UI processor; GLCDC drives RGB interface, DRW2D renders buttons/icons, and RTC maintains event timestamps. Use Value: On-chip 1 MB SRAM eliminates external SDRAM; 2 MB flash stores UI assets and firmware; 5-V tolerant I/O simplifies connection to legacy 5 V sensors and actuators. |
| Smart Energy Meter | Networked PLC Module |
Use Scenario: DIN-rail mounted electricity meter with pulse counting, tariff switching, and remote firmware update via Ethernet. IC Role / Device Role / Timing Role: Precision measurement controller; S12AD units sample current/voltage transformers, RTC manages billing periods, SDHI logs consumption history. Use Value: 12-bit ADC with self-diagnostic ensures metrology accuracy; VBATT-backed RTC guarantees time continuity during mains failure; TSIP secures firmware updates. |
Use Scenario: Compact programmable logic controller with Ethernet I/O expansion, ladder logic execution, and web-based configuration. IC Role / Device Role / Timing Role: Real-time control engine; GPTW timers generate precise PWM outputs for motor control, ELC links encoder interrupts to counter updates. Use Value: 136 GPIOs support direct connection to digital I/O modules; Ethernet MAC + SDHI enables web server hosting and log storage without external memory. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFP#30 | Same die, identical specs, but shipped in PLQP0144KA-B (144-pin LQFP, 20 × 20 mm); 111 GPIOs, no PDC or GLCDC | Suitable for space-constrained designs without camera or LCD requirements; lacks parallel data capture and graphic-LCD controller | Select #30 only if footprint reduction is critical and graphics/CMOS camera interfaces are unused. |
| R5F566TBADFP#10 | Same package (176-pin LQFP), but 1 MB flash (vs. 2 MB), no TSIP, no DRW2D, reduced peripheral set (no QSPI, no second CAN) | Targeted at cost-sensitive control applications without secure boot, advanced graphics, or quad-SPI flash expansion | Choose #10 when dual-bank flash, TSIP, or DRW2D are required; #B variant trades features for lower unit cost. |
Compared with R5F566TEADFP#30 and R5F566TBADFP#10, the R5F566TEADFP#10 uniquely delivers full peripheral complement-including dual-bank 2 MB flash, TSIP, GLCDC, DRW2D, QSPI, and PDC-in the 176-pin LQFP package, making it the only option for feature-complete industrial HMI and gateway designs requiring both Ethernet and rich multimedia support.
Availability
R5F566TEADFP#10 is available at Aetrix Electronics and suitable for industrial gateways, human-machine interfaces, smart energy meters, and networked PLC modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F566TEADFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX66N Group, including the R5F566TEADFP#10, was designed for high-performance industrial automation and networked edge devices-emphasizing real-time determinism, functional safety (IEC 60730), graphics capability, and secure connectivity.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566TEADFP#10?
The R5F566TEADFP#10 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's optimized pipeline, double-precision FPU, and zero-wait-state access to 2 MB flash and 1 MB SRAM-all confirmed in the official R01DS0344EJ0120 datasheet Rev.1.20.
Does the R5F566TEADFP#10 include an integrated Ethernet PHY?
No, the R5F566TEADFP#10 integrates only the Ethernet MAC (ETHERC) and PHY Management Interface (PMGI), not a physical-layer transceiver. An external 10/100 Mbps PHY IC (e.g., LAN8720A) must be used with MII or RMII signaling. The R5F566TEADFP#10 provides all MAC registers, DMA controllers (EDMAC), and clocking required for full Ethernet stack implementation.
What package type and pin count does the R5F566TEADFP#10 use?
The R5F566TEADFP#10 uses the PLQP0176KB-C package: a 176-pin Low-profile Quad Flat Package measuring 24 × 24 mm with 0.5 mm pitch. It provides 136 general-purpose I/O pins, 19 of which are 5-V tolerant-verified in Table 1.2 of the R01DS0344EJ0120 datasheet and Renesas' official package drawings.
Is the R5F566TEADFP#10 supported for IEC 60730 Class B compliance?
Yes, the R5F566TEADFP#10 includes dedicated hardware for IEC 60730 Class B: oscillation-stoppage detection, hardware CRC accelerator (CRCA), independent watchdog timer (IWDTa) with windowing, self-diagnostic A/D converter test, and register write protection. These features are explicitly documented in Section 1.1 and Chapter 42 of the R01DS0344EJ0120 datasheet.
What is the flash memory configuration of the R5F566TEADFP#10?
The R5F566TEADFP#10 contains 2 MB of on-chip code flash memory organized in a dual-bank structure, enabling background programming and startup bank swapping. It also includes 32 KB of reprogrammable data flash rated for 100,000 erase/write cycles-both features confirmed in Table 1.1 and Section 2.2 of the R01DS0344EJ0120 datasheet.
R5F566TEADFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX66T
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 72
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 22x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566TEADFP#10 FAQ
1.How can I place an order for R5F566TEADFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566TEADFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566TEADFP#10 reliable?
The price and inventory of R5F566TEADFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566TEADFP#10 is usually 5 days.
3.What payment methods are accepted for R5F566TEADFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566TEADFP#10 transactions.
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R5F566TEADFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566TEADFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566TEADFP#10?
For technical support, including R5F566TEADFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566TEADFP#10 requirements.
6.How does Aetrix verify that R5F566TEADFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F566TEADFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566TEADFP#10 meets industry standards.
7.What is the process for return or replacement of R5F566TEADFP#10?
All R5F566TEADFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566TEADFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566TEADFP#10 part is unused and in its original packaging.
Return procedure for R5F566TEADFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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