Renesas R5F566TKBDFP#10
- Part No.:
- R5F566TKBDFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F566TKBDFP#10.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:600
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F566TKBDFP#10 from Renesas is a 120 MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 4 MB on-chip code flash (dual-bank), 1 MB SRAM (including 32 KB ECC RAM), and integrated Ethernet MAC, CAN, SDHI, QSPI, and GLCDC. It targets industrial HMI, networked gateways, and real-time control systems requiring deterministic timing, functional safety support (IEC60730), and rich peripheral integration.
For engineers reviewing the R5F566TKBDFP#10 datasheet, R5F566TKBDFP#10 pinout, R5F566TKBDFP#10 application, or R5F566TKBDFP#10 equivalent, this MCU delivers verified dual-bank flash for safe firmware updates, hardware-accelerated 2D graphics rendering via DRW2D, real-time clock with battery backup, and IEC60730-compliant self-test features including oscillation-stop detection and A/D converter diagnostics.
Technical Context
The R5F566TKBDFP#10 implements the RXv3 CPU core with 698 CoreMark at 120 MHz, supporting little-endian or big-endian data arrangement and 113 instructions including DSP and floating-point operations. Its memory subsystem includes 4 MB code flash with 8.3 ns read cycle at full speed, 32 KB data flash rated for 100,000 erase/write cycles, and 1 MB SRAM split into no-wait 512 KB, ECC-protected 32 KB, and 8 KB standby RAM.
Peripheral architecture integrates dedicated DMA controllers (DMACAa: 8 ch, EXDMAC: 2 ch, DTCb: 1 ch), event-linking capability across 123 internal signals, and clock domains segmented by function - ICLK up to 120 MHz for CPU, PCLKA up to 120 MHz for ETHERC/GLCDC/DRW2D, PCLKB up to 60 MHz for timers/A/D, and BCLK up to 80 MHz for external bus access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 698 CoreMark, double-precision IEEE-754 FPU |
| Flash Memory | 4 MB code flash with dual-bank structure enabling background programming and safe bank swap |
| RAM | 1 MB total: 512 KB no-wait SRAM + 512 KB expansion RAM + 32 KB ECC RAM + 8 KB standby RAM |
| Peripherals | Ethernet MAC (10/100 Mbps), CAN (3 channels, 32 mailboxes each), SDHI (25 MB/s), QSPI, GLCDC, DRW2D, PDC, 12-bit A/D (29 ch), 12-bit D/A (2 ch) |
| Security & Safety | TSIP optional encryption (AES-128/192/256), IEC60730 compliance features: CRC, IWDT, oscillator-stop detection, A/D self-diagnostic |
| Package | LFBGA-176 (PLQP0176KB-C), 24 × 24 mm, 0.5 mm pitch, –40°C to +85°C operating range |
| Power Supply | Single 2.7–3.6 V supply; RTC supports dedicated VBATT backup |
Pinout & Package
Package: PLQP0176KB-C - 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 24 mm × 24 mm, 0.5 mm ball pitch, RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Three independent 2.7–3.6 V supplies; AVCC0/AVCC1 feed A/D and analog circuits with separate filtering paths |
| VBATT | Battery backup input | Enables RTC operation during main power loss; requires external coin-cell or supercapacitor |
| RES# | Active-low reset input | Asynchronous hardware reset; low pulse ≥ 100 ns triggers full system reset |
| CLKIN / CLKOUT | External crystal interface | Supports 8–24 MHz crystal or external clock; CLKOUT provides buffered system clock output |
| ETXD0–7 / ETRD0–7 / ETMDIO / ETMDC | Ethernet PHY interface | MII/RMII-compliant 8-bit parallel data bus + MDIO/MDC for PHY management |
| TXD0 / RXD0 / RTS0 / CTS0 | SCI0 UART interface | Full-duplex asynchronous serial port with hardware flow control; supports LIN protocol on SCIh |
| SDCLK / SDCMD / SDDAT0–3 | SD host interface | 4-bit SD bus supporting high-speed mode (25 MB/s); includes card detect and write protect inputs |
| QSPI_IO0–3 / QSPI_CLK / QSPI_CS | Quad SPI interface | Configurable for single/dual/quad I/O modes; supports XIP (execute-in-place) from external flash |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank code flash | Enables seamless firmware updates without halting execution; one bank runs while the other is reprogrammed |
| Hardware 2D drawing engine (DRW2D) | Accelerates vector graphics (lines, triangles, circles) and bit-blit operations (copy, stretch, rotate) without CPU load |
| Event Link Controller (ELC) | Direct hardware interconnection of 123 internal peripherals eliminates CPU polling and interrupt latency for time-critical sequences |
| IEC60730-compliant safety functions | Includes CRC calculation unit, independent watchdog timer (IWDT), oscillation-stop detection, and A/D self-diagnostic |
| Graphic LCD controller (GLCDC) | Supports 3-layer overlay (background + 2 graphics planes), 32/16 bpp formats, and CLUT-based color conversion |
| Parallel Data Capture (PDC) | Acquires CMOS camera frames using external HSYNC/VSYNC; supports clipping and direct frame buffer DMA |
Applications
| Industrial HMI Gateway | Networked Building Controller |
|---|---|
|
Use Scenario: Central gateway aggregating Modbus RTU, CANopen, and BACnet MS/TP field devices into Ethernet/IP or MQTT networks. IC Role / Device Role / Timing Role: Real-time protocol translation engine with deterministic Ethernet MAC + CAN + SCI timing, backed by 120 MHz RXv3 core and dual-bank flash for OTA updates. Use Value: Eliminates need for external FPGA or co-processor; DRW2D renders local touch UI while ETHERC handles cloud telemetry. |
Use Scenario: HVAC controller managing chillers, AHUs, and VAV boxes with embedded web server and secure remote access. IC Role / Device Role / Timing Role: Integrated security anchor with TSIP AES encryption, IEC60730 diagnostics, and RTC-backed logging for audit compliance. Use Value: Meets UL 60730 Class B requirements out-of-box; ECC RAM prevents silent data corruption in critical control loops. |
| Smart Energy Meter Hub | Factory Automation Edge Node |
|
Use Scenario: Multi-tariff electricity meter with PLC/G3-PLC backhaul, tamper detection, and encrypted firmware updates. IC Role / Device Role / Timing Role: Secure metering SoC with 12-bit A/D (29 ch) for voltage/current sensing, SDHI for secure log storage, and QSPI for trusted boot image. Use Value: TSIP enables hardware-accelerated AES-256 for DLMS/COSEM encryption; dual-bank flash ensures zero-downtime field upgrades. |
Use Scenario: Vision-guided robotic cell controller acquiring images from CMOS sensors and executing motion profiles via GPTW PWM outputs. IC Role / Device Role / Timing Role: Real-time vision processor with PDC for camera capture, DRW2D for ROI processing, and MTU3a/TPUa for synchronized servo control. Use Value: Hardware event linking (ELC) synchronizes image capture trigger with PWM edge, achieving sub-microsecond jitter between vision and actuation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TJHDFP#10 | Same RX66N Group, 144-pin LFQFP package (PLQP0144KA-B), 2 MB flash, 512 KB SRAM | Lower pin count and memory; lacks SDHI, QSPI, and GLCDC; suitable for cost-sensitive non-HMI designs | Select when board space constraints favor QFP and graphics/Ethernet are unnecessary |
| R5F566TKCDFP#10 | Same 176-pin LFBGA package but with 2 MB flash and 512 KB SRAM; identical peripheral set except reduced A/D channels (16 ch) | Matches footprint and pinout but trades flash/SRAM capacity for lower BOM cost in non-firmware-intensive roles | Choose for identical layout reuse where 4 MB flash and full 29-channel A/D are not required |
Compared with R5F566TKBDFP#10, the R5F566TJHDFP#10 reduces package size and memory to cut cost in simpler gateways, while the R5F566TKCDFP#10 maintains identical LFBGA-176 compatibility but scales down flash and A/D resources - both serve as validated alternatives when full 4 MB/29-ch capability is over-provisioned.
Availability
R5F566TKBDFP#10 is available at Aetrix Electronics and suitable for industrial HMI gateways, networked building controllers, smart energy meter hubs, and factory automation edge nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F566TKBDFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX66N Group, including R5F566TKBDFP#10, was designed for high-performance industrial applications demanding real-time responsiveness, functional safety, rich connectivity (Ethernet/CAN/SD/QSPI), and embedded graphics - targeting HMI, gateway, and edge-control use cases.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566TKBDFP#10?
The R5F566TKBDFP#10 operates at a maximum frequency of 120 MHz and achieves 698 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's optimized instruction pipeline, double-precision FPU, and zero-wait-state 4 MB flash access - enabling deterministic real-time execution in industrial control loops and protocol stacks.
Does the R5F566TKBDFP#10 support dual-bank flash for safe firmware updates?
Yes, the R5F566TKBDFP#10 includes a dual-bank code flash architecture that allows background programming of one bank while executing from the other. This enables robust over-the-air (OTA) updates without system interruption - a key requirement for certified industrial gateways and remote infrastructure equipment using R5F566TKBDFP#10.
What peripheral interfaces does the R5F566TKBDFP#10 include for industrial connectivity?
The R5F566TKBDFP#10 integrates Ethernet MAC (10/100 Mbps MII/RMII), three CAN channels (ISO11898-1 compliant, 32 mailboxes each), SD host interface (25 MB/s), quad SPI, and multiple SCI/RSPI ports. These interfaces enable direct connection to fieldbus networks, cloud uplinks, secure storage, and high-bandwidth peripherals - all within a single R5F566TKBDFP#10 device.
How does the R5F566TKBDFP#10 meet IEC60730 functional safety requirements?
The R5F566TKBDFP#10 includes hardware features mandated by IEC60730 Class B: oscillation-stop detection, independent watchdog timer (IWDT), CRC calculation unit, self-diagnostic A/D test mode, and register write protection. These are documented in Renesas' Functional Safety Manual for RX66N and validated for use in R5F566TKBDFP#10-based safety-critical control applications.
What is the package type and thermal specification of the R5F566TKBDFP#10?
The R5F566TKBDFP#10 uses the PLQP0176KB-C package: a 176-ball LFBGA with 24 mm × 24 mm footprint and 0.5 mm pitch. It is rated for industrial temperature range (–40°C to +85°C), with thermal resistance (θJA) of 22.5°C/W and recommended PCB layout per Renesas AN1900 application note to ensure reliable operation at 120 MHz.
R5F566TKBDFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX66T
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 73
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 22x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566TKBDFP#10 FAQ
1.How can I place an order for R5F566TKBDFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566TKBDFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566TKBDFP#10 reliable?
The price and inventory of R5F566TKBDFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566TKBDFP#10 is usually 5 days.
3.What payment methods are accepted for R5F566TKBDFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F566TKBDFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F566TKBDFP#10?
R5F566TKBDFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566TKBDFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566TKBDFP#10?
For technical support, including R5F566TKBDFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566TKBDFP#10 requirements.
6.How does Aetrix verify that R5F566TKBDFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F566TKBDFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566TKBDFP#10 meets industry standards.
7.What is the process for return or replacement of R5F566TKBDFP#10?
All R5F566TKBDFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566TKBDFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566TKBDFP#10 part is unused and in its original packaging.
Return procedure for R5F566TKBDFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F566TKBDFP#10 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

