Renesas R5F566TKCGFB#30
- Part No.:
- R5F566TKCGFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F566TKCGFB#30.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:175
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Product details
Overview
R5F566TKCGFB#30 from Renesas is a 32-bit RXv3 microcontroller optimized for motor control and industrial real-time applications, operating at up to 160 MHz with 928 CoreMark performance, 1 MB on-chip code flash, 128 KB SRAM (no wait states), and integrated 3-phase/5-phase complementary PWM generation. It features dual 12-bit A/D converters with simultaneous sampling across 30 channels, 6-channel analog comparators, 2-channel 12-bit D/A converters, and hardware-accelerated AES-128/256 encryption via TSIP-Lite - deployed in servo drives, inverters, and PLC I/O modules.
For engineers reviewing the R5F566TKCGFB#30 datasheet, R5F566TKCGFB#30 pinout, R5F566TKCGFB#30 application, or R5F566TKCGFB#30 equivalent, key selection criteria include its 144-pin LFQFP package with 110 GPIOs (4× 5-V tolerant), 160-MHz GPTW timer with 195-ps HRPWM resolution, CAN 2.0B compliance, full-speed USB 2.0 host/function capability, and IEC 60730 safety support including oscillation-stop detection, RAM ECC, and CRC acceleration.
Technical Context
The R5F566TKCGFB#30 implements the RXv3 CPU core with single-cycle instruction execution, IEEE 754-compliant FPU, and configurable endianness. Its clock system integrates PLL, high-speed on-chip oscillator (16–20 MHz), low-speed oscillator (240 kHz), and independent IWDT-dedicated 120-kHz oscillator - enabling precise timing control for motor phase alignment and safety-critical watchdog supervision.
Peripheral coordination is managed through the Event Link Controller (ELC), which interconnects 188 internal event signals without CPU intervention - allowing synchronized A/D conversion triggers from GPTW/MTU3 timers, automatic dead-time insertion during PWM fault conditions, and autonomous comparator-to-GPIO state transitions in deep software standby mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 160 MHz max operation, 928 CoreMark, single-cycle instruction execution, IEEE 754 FPU |
| Memory | 1 MB code flash (no wait cycles ≤120 MHz), 128 KB SRAM (no wait states), 32 KB data flash (100k erase/write cycles), 16 KB ECC SRAM |
| PWM & Timers | 10× 32-bit GPTW channels + 9× 16-bit MTU3d channels + 4× HRPWM (195 ps min resolution at 160 MHz) |
| Analog Peripherals | 30-channel 12-bit S12ADH ADC (3 units, simultaneous sampling), 6-channel CMPC, 2× 12-bit R12DAb DAC, PGA with pseudo-differential input |
| Communication | CAN 2.0B (32 mailboxes), full-speed USB 2.0 host/function/OTG, 7× SCI (including LIN-capable SCIh), 1× RIIC (400 kbps), 1× RSPI (30 Mbps) |
| Safety & Security | IEC 60730 support: CAC clock accuracy monitor, LVDA voltage detection, DOC RAM test assist, CRCA CRC engine, TSIP-Lite AES-128/256 + TRNG |
| Package & Environment | 144-pin LFQFP (PLQP0144KA-B), 20 × 20 mm, 0.5 mm pitch, –40°C to +105°C (G-version), 2.7–5.5 V supply |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.5 mm lead pitch, exposed thermal pad, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual power domains: VCC (2.7–5.5 V), AVCC0/1/2 (3.0–5.5 V), VCC_USB (3.0–3.6 V when USB active) |
| XTAL / EXTAL | Main clock oscillator interface | Supports 8–24 MHz crystal/resonator; enables PLL reference for 160 MHz system clock |
| MTIOC0A–MTIOC9A | MTU3 waveform I/O | 9-channel complementary PWM output with programmable dead time, phase counting, and synchronous start/stop |
| GTIOCA0–GTIOCA9 | GPTW waveform I/O | 10-channel high-resolution PWM outputs with 195 ps timing control and fault-triggered output disable |
| ADTRG0–ADTRG2 | A/D conversion trigger inputs | Hardware-synchronized start of 12-bit S12ADH conversion from timer, ELC, or external signal |
| TXD0 / RXD0 | SCI0 serial interface | Asynchronous UART mode with programmable baud rate, noise filtering, and ELC-linked interrupt generation |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical layer | Full-speed (12 Mbps) transceiver with integrated PHY, 2 KB on-chip buffer, no external pull-up required |
| CTX0 / CRX0 | CAN bus interface | ISO 11898-1 compliant differential transceiver interface supporting standard/extended frames and 32 mailbox FIFO |
Key Features
| Feature | Design Value |
|---|---|
| High-resolution PWM timing | HRPWM achieves 195 ps minimum edge placement resolution on GPTW0–GPTW3 outputs - enabling precise dead-time control for SiC/GaN inverter gate drivers |
| Simultaneous multi-unit A/D sampling | Three independent 12-bit S12ADH units support concurrent sampling across 30 channels with shared trigger - critical for vector-controlled motor current sensing |
| Event-driven peripheral coordination | ELC links 188 internal events (e.g., GPTW compare match → A/D start → CMPC output → GPIO toggle) without CPU overhead or interrupt latency |
| IEC 60730 Class B compliance support | Integrated hardware blocks include CAC clock monitor, LVDA voltage detectors, DOC-assisted RAM test, CRCA checksum engine, and register write protection |
| Secure firmware execution | Trusted Memory (TM) locks blocks 8–9 of code flash against read-out; TSIP-Lite provides AES-128/256 encryption, TRNG, and key isolation for secure boot and OTA updates |
Applications
| Industrial Servo Drives | EV Onboard Chargers (OBC) |
|---|---|
|
Use Scenario: Real-time field-oriented control (FOC) of PMSM/BLDC motors with dual-shunt current sensing and thermal monitoring. IC Role / Device Role / Timing Role: Primary motor control MCU executing FOC loop at ≤10 µs intervals, synchronizing PWM, ADC, and comparator events via ELC. Use Value: 160 MHz GPTW + 195 ps HRPWM enables <100 ns dead-time tuning for SiC MOSFETs; simultaneous 30-channel ADC captures phase currents and DC-link voltage in one cycle. |
Use Scenario: Digital control of AC/DC and DC/DC stages in bidirectional OBCs with grid synchronization and isolation monitoring. IC Role / Device Role / Timing Role: System controller managing rectifier PFC, LLC resonant converter, and battery charging profiles using hardware-timed PWM and safety-checked ADC. Use Value: Integrated CAN 2.0B interfaces with vehicle network; TSIP-Lite secures firmware updates; IEC 60730 functions validate clock, memory, and analog subsystems per UL 62368-1. |
| Programmable Logic Controllers (PLC) | Industrial HVAC Inverters |
|
Use Scenario: High-density digital I/O expansion with analog sensor integration, motion control, and EtherCAT slave stack execution. IC Role / Device Role / Timing Role: Central processing unit handling cyclic process data exchange, local motion sequencing, and safety logic in parallel with communication stacks. Use Value: 110 GPIOs (4× 5-V tolerant) support mixed-voltage I/O; USB 2.0 OTG enables field configuration via PC; ECC SRAM ensures deterministic runtime integrity. |
Use Scenario: Variable-frequency control of centrifugal chillers and air-handling units with refrigerant pressure/temperature feedback and fan speed modulation. IC Role / Device Role / Timing Role: Dedicated inverter controller generating 3-phase/5-phase complementary PWM while monitoring compressor vibration and ambient conditions. Use Value: 6-channel CMPC detects overcurrent faults within 100 ns; temperature sensor + 12-bit ADC enable closed-loop thermal derating; 40 MHz external bus supports fast display interface. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar motor control MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TECGFB#30 | Same RX66T family, identical 144-pin LFQFP package, but with 512 KB code flash and 64 KB SRAM (vs. 1 MB / 128 KB) | Targeted at cost-sensitive servo drives with reduced firmware footprint and lower memory bandwidth requirements | Select when application firmware size < 400 KB and real-time data buffering needs ≤64 KB SRAM |
| R5F566TKCDFA#30 | Same 1 MB flash / 128 KB SRAM spec, but in 100-pin LFQFP (PLQP0100KB-B), 14 × 14 mm, 0.5 mm pitch - 44 fewer pins | Used in space-constrained inverters where GPIO count reduced to 69 and USB/CAN co-location not required | Select when board area is constrained and peripheral count (e.g., SCI channels, ADC inputs) can be reduced by ≥30% |
Compared with R5F566TKCGFB#30, the R5F566TECGFB#30 offers identical timing and safety features at lower memory density, while the R5F566TKCDFA#30 maintains full memory capacity in a smaller footprint but sacrifices 41 GPIOs and removes USB functionality - making the original optimal for full-featured, high-I/O industrial controllers.
Availability
R5F566TKCGFB#30 is available at Aetrix Electronics and suitable for industrial servo drives, EV onboard chargers, and programmable logic controllers requiring stable component supply, long-term lifecycle assurance, and automotive-grade temperature range (–40°C to +105°C).
Supply support for R5F566TKCGFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise applications.
The RX66T Group - to which R5F566TKCGFB#30 belongs - was designed specifically for real-time motor control and industrial automation, integrating high-precision PWM, safety-certified peripherals, and deterministic interrupt response to replace legacy DSP-based systems.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F566TKCGFB#30?
The R5F566TKCGFB#30 operates at a maximum frequency of 160 MHz and achieves 928 CoreMark performance under benchmark conditions. This reflects its RXv3 CPU core efficiency, on-chip cache behavior, and memory subsystem bandwidth - all validated per R01DS0315EJ0130 Rev.1.30. The R5F566TKCGFB#30 sustains this performance across its full operating temperature range (–40°C to +105°C) with no derating.
Does the R5F566TKCGFB#30 support IEC 60730 Class B compliance out of the box?
Yes, the R5F566TKCGFB#30 includes dedicated hardware for IEC 60730 Class B compliance: oscillation-stop detection, clock frequency accuracy measurement (CAC), RAM test assistance via DOC, CRC calculation (CRCA), independent watchdog timer (IWDTa), and register write protection. These features are documented in the R01DS0315EJ0130 datasheet and require no external components to implement basic self-test sequences.
What PWM resolution does the R5F566TKCGFB#30 achieve, and how is it implemented?
The R5F566TKCGFB#30 achieves a minimum PWM edge placement resolution of 195 ps using its HRPWM circuit, which overlays fine timing control onto the 32-bit GPTW0–GPTW3 outputs. This resolution is realized at 160 MHz system clock and enables sub-nanosecond dead-time tuning - essential for minimizing shoot-through in SiC/GaN-based inverter designs. The R5F566TKCGFB#30 implements this via dedicated HRPWM registers synchronized to PCLKC.
How many analog-to-digital converter channels does the R5F566TKCGFB#30 support, and what is their sampling capability?
The R5F566TKCGFB#30 integrates three 12-bit S12ADH units totaling 30 input channels: Unit 0 (8 channels), Unit 1 (8 channels), and Unit 2 (14 channels). It supports simultaneous sampling across all units using shared hardware triggers, with minimum conversion time of 0.9 µs per channel at 60 MHz ADCLK. Each unit includes dedicated sample-and-hold circuits (3 per unit for Units 0/1), and Unit 2 incorporates the on-die temperature sensor.
Is the R5F566TKCGFB#30 pin-compatible with other RX66T group MCUs in the same package?
No - the R5F566TKCGFB#30 is not universally pin-compatible across all RX66T variants in the 144-pin LFQFP package. While it shares the PLQP0144KA-B mechanical footprint with other 144-pin RX66T devices, pin functions differ based on flash/SRAM configuration and peripheral enablement (e.g., USB presence affects pin allocation). Pin mapping must be verified per device-specific section of R01DS0315EJ0130; R5F566TKCGFB#30's full 110-GPIO capability requires its specific memory and feature set.
R5F566TKCGFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, LINbus, MMC/SD, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 110
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 30x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F566TKCGFB#30 FAQ
1.How can I place an order for R5F566TKCGFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F566TKCGFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F566TKCGFB#30 reliable?
The price and inventory of R5F566TKCGFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F566TKCGFB#30 is usually 5 days.
3.What payment methods are accepted for R5F566TKCGFB#30?
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R5F566TKCGFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F566TKCGFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F566TKCGFB#30?
For technical support, including R5F566TKCGFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F566TKCGFB#30 requirements.
6.How does Aetrix verify that R5F566TKCGFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F566TKCGFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F566TKCGFB#30 meets industry standards.
7.What is the process for return or replacement of R5F566TKCGFB#30?
All R5F566TKCGFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F566TKCGFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F566TKCGFB#30 part is unused and in its original packaging.
Return procedure for R5F566TKCGFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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