Renesas R5F56719DDFB#10
- Part No.:
- R5F56719DDFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F56719DDFB#10.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F56719DDFB#10 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SDHI, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control, secure firmware updates, and low-power operation.
For engineers reviewing the R5F56719DDFB#10 datasheet, R5F56719DDFB#10 pinout, R5F56719DDFB#10 application, or R5F56719DDFB#10 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-B (144-pin LFQFP), functional pin roles, IEC60730-compliant safety features, and validated alternative MCUs for migration or second-sourcing.
Technical Context
The R5F56719DDFB#10 implements the RXv3 CPU core with 113 instructions, including 21 double-precision FPU ops and DSP extensions, supporting little-endian or big-endian data arrangement and register bank save across 16 banks. It integrates a memory protection unit (MPU) with eight configurable regions (min. 16-byte granularity) and supports TrustZone-like isolation via Trusted Memory (TM) for secure code execution.
Its clock architecture uses independent PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and sub-clock (32.768 kHz) sources, enabling asynchronous domain control: ICLK up to 120 MHz for CPU/QSPIX, PCLKA up to 120 MHz for MTU/RSPI/RIICHS, and PCLKB up to 60 MHz for most peripherals and ADC clocks - ensuring deterministic timing for mixed-criticality tasks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark, double-precision FPU per IEEE-754 |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k cycles), 384 KB SRAM (no-wait @120 MHz) |
| Peripherals | 2× CAN (ISO11898-1, 32 mailboxes/channel), 1× USB 2.0 FS host/function/OTG, 1× SDHI (25 MB/s), 1× QSPIX (fetch from serial flash) |
| Analog & Timing | Two 12-bit S12AD units (8+12 ch), RTC with battery backup, 32-bit CMTW timers, IWDTa with window function |
| Security & Interface | TSIP crypto engine (AES128/192/256, RSA, ECC, TRNG, SHA256), 114 GPIO (20× 5-V tolerant), CTSU (17 self-capacitance keys) |
| Power & Environment | 2.7–3.6 V supply, –40°C to +85°C (D-version), four low-power modes including deep software standby with 4 KB backup RAM |
Pinout & Package
Package: PLQP0144KA-B - 144-pin LQFP, 20 × 20 mm, 0.50-mm pitch, RoHS-compliant, lead-free, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains for digital logic and ADC reference stability; AVCC1 powers S12AD unit 1 |
| VBATT | Backup power input | Enables RTC, sub-clock oscillator, and backup registers during main power loss; requires external coin-cell or capacitor |
| XTAL/EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal; enables precise system clock generation and oscillation-stop detection |
| RTCIN/RTCOUT | 32.768 kHz sub-clock interface | Connects to external tuning-fork crystal for battery-backed real-time clock with ±3 ppm accuracy |
| TXD0/RXD0 | SCI0 UART interface | Dedicated asynchronous serial channel for bootloader communication or debug console (supports LIN protocol) |
| USB_VBUS, USB_DP, USB_DM | USB 2.0 full-speed transceiver | Integrated PHY eliminates external transceiver; VBUS detection enables host/device role negotiation and OTG switching |
| SD_CLK, SD_CMD, SD_DAT0–3 | SD host interface signals | Direct 4-bit SD bus connection to SD memory or SDIO cards; supports high-speed mode (25 MB/s) and CRC16 error checking |
| QSPIX_IO0–3, QSPIX_CLK, QSPIX_CS | Quad-SPI memory interface | Enables XIP (execute-in-place) from external serial flash; supports extended/dual/quad SPI protocols with 32-bit addressing |
Key Features
| Feature | Design Value |
|---|---|
| Trusted Secure IP (TSIP) | Hardware-accelerated AES/RSA/ECC encryption, true random number generation, and key protection prevent firmware cloning and side-channel attacks |
| Dual-bank flash with BGO | Enables seamless firmware updates: new code writes to inactive bank while active bank executes; bank swap occurs on reset without downtime |
| IEC60730 Class B compliance support | Includes CRC accelerator, oscillation-stop detection, IWDTa windowing, A/D self-diagnostic, and register write protection for safety-critical firmware |
| Capacitive Touch Sensing Unit (CTSU) | Supports 17-key self-capacitance or 64-key mutual-capacitance matrix without external components - ideal for sealed industrial HMI panels |
| Event Link Controller (ELC) | 99 internal event signals routed without CPU intervention - e.g., TPU PWM output triggers ADC conversion, reducing jitter and ISR latency |
Applications
| Industrial HMI Panel | Smart Electricity Meter |
|---|---|
Use Scenario: Embedded touchscreen controller in DIN-rail mounted panel with CAN fieldbus connectivity and local data logging. IC Role / Device Role / Timing Role: Main application processor executing RTOS, managing capacitive touch UI, driving SD card logging, and synchronizing CAN message timing via MTU3a PWM-triggered ADC sampling. Use Value: Dual-bank flash enables remote firmware updates over CAN without interrupting metering functions; TSIP secures OTA update integrity. |
Use Scenario: Revenue-grade meter with tamper detection, real-time energy calculation, and PLC/RF communication co-processor interface. IC Role / Device Role / Timing Role: System controller handling metrology data aggregation, RTC-based billing intervals, tamper event timestamping, and secure key management for DLMS/COSEM. Use Value: Backup RAM retains critical billing counters during brownouts; temperature sensor compensates ADC gain drift across –40°C to +85°C operating range. |
| Home Energy Gateway | Factory Automation Edge Node |
Use Scenario: Residential gateway aggregating Zigbee/Z-Wave sensors, exposing data via USB-connected PC or SDHI-stored logs. IC Role / Device Role / Timing Role: Central hub MCU running lightweight Linux or FreeRTOS, bridging wireless protocols to USB host (for PC tethering) and SDHI (for local history storage). Use Value: Integrated USB 2.0 FS host eliminates external PHY; QSPIX fetches boot image from serial NOR, reducing BOM cost and footprint. |
Use Scenario: Compact PLC I/O module with CANopen master, isolated digital inputs, and local diagnostics display. IC Role / Device Role / Timing Role: Real-time controller executing cyclic CANopen PDO exchange, sampling 12-bit analog inputs via S12AD unit 1, and updating segmented LCD via GPIO bit-banging. Use Value: 114 GPIO pins support mixed signal I/O; CMTW timers provide µs-accurate cycle synchronization for deterministic CANopen timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F56709DDFB#10 | Same RX671 Group, 1 MB flash (vs. 2 MB), identical pinout and peripheral set except reduced SRAM (256 KB vs. 384 KB) | Suitable for cost-sensitive designs where firmware size < 1 MB and buffer requirements are lower | Select when full 2 MB flash and 384 KB SRAM are not required; maintains drop-in compatibility on PLQP0144KA-B layout |
| R5F572N9DDFB#10 | RX72N Group part: higher 240 MHz CPU, 4 MB flash, but different pinout (144-pin TFLGA), no SDHI or QSPIX, adds Ethernet MAC | Better for networked edge controllers needing TCP/IP stack, but requires PCB redesign and lacks serial flash boot capability | Choose only if Ethernet connectivity is mandatory and flash/SRAM scaling justifies board revision and toolchain migration |
Compared with R5F56719DDFB#10, R5F56709DDFB#10 offers identical peripheral functionality at lower memory cost with zero layout change, while R5F572N9DDFB#10 trades serial memory interface and SD support for Ethernet - making it unsuitable for flash-booted or SD-dependent deployments without hardware rework.
Availability
R5F56719DDFB#10 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, home energy gateways, and factory automation edge nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F56719DDFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a Japan-based semiconductor manufacturer specializing in microcontrollers, analog, and power solutions for industrial, automotive, and IoT markets.
The RX671 Group - including R5F56719DDFB#10 - is engineered for high-integrity industrial applications demanding real-time performance, functional safety (IEC60730), secure firmware, and rich connectivity (CAN, USB, SDHI, QSPIX) in compact packages.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F56719DDFB#10?
The R5F56719DDFB#10 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark points under benchmark conditions. This performance stems from its RXv3 CPU core with dual-issue pipeline, on-chip 32-bit multiplier/divider, and optimized instruction set - enabling deterministic real-time response in industrial control loops without external acceleration.
Does the R5F56719DDFB#10 support secure firmware updates and cryptographic operations?
Yes, the R5F56719DDFB#10 integrates Trusted Secure IP (TSIP) with hardware-accelerated AES128/192/256, RSA, ECC, SHA256, and a true random number generator. It supports secure boot, encrypted firmware updates via dual-bank flash, and key protection against extraction - meeting IEC60730 Class B requirements for safe field upgrades.
What package type and pin count does the R5F56719DDFB#10 use?
The R5F56719DDFB#10 uses the PLQP0144KA-B package: a 144-pin LQFP measuring 20 × 20 mm with 0.50-mm pitch. It provides 114 general-purpose I/O pins (20 of which are 5-V tolerant), and shares pin compatibility with other RX671 variants in the same package family - simplifying design reuse across memory configurations.
Can the R5F56719DDFB#10 boot directly from external serial flash memory?
Yes, the R5F56719DDFB#10 supports execute-in-place (XIP) booting from external serial flash via its QSPIX interface. The QSPIX controller handles extended, dual-, and quad-SPI protocols with 32-bit addressing, enabling fast, low-pin-count boot images - eliminating need for large on-chip flash while maintaining deterministic startup timing.
What analog capabilities does the R5F56719DDFB#10 offer for sensor interfacing?
The R5F56719DDFB#10 integrates two independent 12-bit A/D converters (S12AD units): one with 8 channels, another with 12 channels. Each supports 8/10/12-bit resolution, 0.42–0.48 µs conversion time, self-diagnostic voltage generation, analog input disconnection detection, and trigger sources including MTU/TPU timers - ideal for precision metrology and multi-sensor monitoring.
R5F56719DDFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 113
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F56719DDFB#10 FAQ
1.How can I place an order for R5F56719DDFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F56719DDFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F56719DDFB#10 reliable?
The price and inventory of R5F56719DDFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F56719DDFB#10 is usually 5 days.
3.What payment methods are accepted for R5F56719DDFB#10?
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R5F56719DDFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F56719DDFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F56719DDFB#10?
For technical support, including R5F56719DDFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F56719DDFB#10 requirements.
6.How does Aetrix verify that R5F56719DDFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F56719DDFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F56719DDFB#10 meets industry standards.
7.What is the process for return or replacement of R5F56719DDFB#10?
All R5F56719DDFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F56719DDFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F56719DDFB#10 part is unused and in its original packaging.
Return procedure for R5F56719DDFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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