Renesas R5F56719DGFP#10
- Part No.:
- R5F56719DGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F56719DGFP#10.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F56719DGFP#10 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control, secure firmware updates, and low-power operation.
For engineers reviewing the R5F56719DGFP#10 datasheet, R5F56719DGFP#10 pinout, R5F56719DGFP#10 application, or R5F56719DGFP#10 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-B (144-pin LFQFP), functional pin roles, IEC60730-compliant safety features, and two validated alternative MCUs for migration or second-sourcing decisions.
Technical Context
The R5F56719DGFP#10 implements the RXv3 CPU core with 113 instructions, including DSP and floating-point extensions, and supports little-endian or big-endian data arrangement. It integrates a memory protection unit (MPU) with eight configurable regions and a Trusted Secure IP (TSIP) engine supporting AES128/192/256, RSA, ECC, SHA256, and TRNG for secure boot and firmware encryption.
Its clock system combines external crystal (8–24 MHz), sub-clock (32.768 kHz), and internal oscillators (LOCO/HOCO/IWDT-dedicated), enabling independent domain clocks: ICLK up to 120 MHz for CPU/QSPIX, PCLKA up to 120 MHz for MTU/RSPI/RIICHS, and PCLKB up to 60 MHz for most peripherals and ADCs - ensuring deterministic timing across mixed-criticality subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max - delivers 707 CoreMark; supports double-precision FPU and register bank save for fast context switching. |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k write cycles), 384 KB SRAM (no wait states), 4 KB standby RAM. |
| Peripherals | 2× CAN (ISO11898-1, 32 mailboxes/channel), 1× USB 2.0 FS host/function/OTG, 1× SDHI (25 MB/s), 1× QSPIX (quad-SPI fetch), 13× SCI, 3× RSPI, 3× RIIC/RIICHS (up to 3.4 Mbps). |
| Analog & Sensing | Two 12-bit S12AD units (8+12 channels), on-chip temperature sensor (±1°C), CTSU capacitive touch unit (17 self-capacitance keys or 64 mutual-capacitance keys). |
| Security & Safety | TSIP crypto engine (AES/RSA/ECC/SHA256/TRNG), MPU, CRC accelerators, IWDT with window function, and IEC60730 self-test functions (ADC diagnosis, oscillator stop detection). |
| Power & Temp | 2.7–3.6 V supply, four low-power modes (deep software standby with VBATT backup), –40°C to +85°C (D-version), PLQP0144KA-B package (20 × 20 mm, 0.50 mm pitch). |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.50 mm pitch, lead-free, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Core & analog power supply | 3.3 V nominal; separate analog domains enable noise-isolated ADC operation and independent voltage monitoring (LVDA). |
| VBATT | Backup power input | Supplies RTC, backup registers, and sub-clock oscillator during main power loss - enables tamper-resistant timekeeping. |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; paired with PLL for stable 120 MHz ICLK generation and clock failure detection. |
| RES# | Active-low reset input | Hardware reset assertion; combined with POR and LVD circuits to ensure reliable startup under varying supply conditions. |
| USB_DP/USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates external PHY; supports host/function/OTG without pull-up resistors. |
| SD_CLK/SD_CMD/SD_DAT[0:3] | SD host interface signals | Direct connection to SD/SDIO cards; supports 4-bit bus mode and high-speed (25 MB/s) transfers with CRC7/CRC16 error checking. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed via background operation (BGO), eliminating runtime interruption. |
| Trusted Secure IP (TSIP) | Hardware-accelerated AES256/SHA256/RSA/ECC and true random number generation - meets IEC62443-3-3 SL2 requirements for secure boot and key protection. |
| Event Link Controller (ELC) | 99 internal event signals routed without CPU intervention - e.g., TPU timer overflow triggers ADC conversion or MTU PWM output toggles GPIO pins synchronously. |
| Capacitive Touch Sensing Unit (CTSU) | Self- and mutual-capacitance modes with built-in noise rejection - supports up to 64-key matrix HMI with no external components, certified per IEC61000-4-6 Level 3. |
| IEC60730 Class B compliance support | Includes oscillator stop detection, CRC calculation unit, IWDT windowing, ADC self-diagnostic, and register write protection - reduces certification effort for household appliances. |
Applications
| Industrial HMI Panel | Smart Energy Meter |
|---|---|
|
Use Scenario: A wall-mounted display with touch interface, real-time energy monitoring, and local data logging over CAN/RS485. IC Role / Device Role / Timing Role: Main application controller managing CTSU touch input, SDHI-based logging, dual CAN for utility communication, and RTC-backed time-stamped events. Use Value: Dual-bank flash allows remote firmware updates without interrupting metering; TSIP secures OTA update integrity and prevents cloning. |
Use Scenario: DIN-rail mounted electricity meter with tariff switching, tamper detection, and secure DLMS/COSEM protocol stack. IC Role / Device Role / Timing Role: System-on-chip controller executing metrology algorithms, managing secure crypto operations, and interfacing with isolated RS485 and optical port. Use Value: Integrated TSIP accelerates AES-128 encryption for DLMS; backup RAM + VBATT preserves critical logs during power outage. |
| Home Automation Gateway | Medical Patient Monitor |
|
Use Scenario: Central hub aggregating Zigbee/Z-Wave sensors, exposing REST API over Ethernet/USB, and driving local LCD + capacitive buttons. IC Role / Device Role / Timing Role: Application processor running FreeRTOS, handling USB CDC/ACM for PC comms, QSPIX for external flash firmware storage, and CTSU for UI navigation. Use Value: 120 MHz RXv3 core handles concurrent protocol stacks; 384 KB SRAM accommodates multiple TLS sessions and UI frame buffers. |
Use Scenario: Portable vital signs monitor with ECG front-end, OLED display, Bluetooth LE, and battery-backed data retention. IC Role / Device Role / Timing Role: Real-time controller acquiring analog sensor data via S12AD, performing filtering in FPU, encrypting data with TSIP, and managing low-power sleep cycles. Use Value: On-chip temperature sensor calibrates ADC offset drift; deep software standby mode extends battery life beyond 72 hours. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F56709DFB#30 | Same RX671 Group, 100-pin TFLGA (7 × 7 mm), 1 MB flash, 256 KB SRAM, no SDHI or QSPIX - lacks SD/serial flash boot capability. | Suitable for space-constrained, cost-sensitive designs where SD card logging or external quad-SPI flash is unnecessary. | Select when PCB area < 50 mm² and peripheral count is reduced; verify pin compatibility using Renesas Pin Migration Tool. |
| R5F566TEBDFP#30 | RX66T Group, 144-pin LFQFP, 120 MHz, 1 MB flash, 192 KB SRAM, optimized for motor control (3× MTU3, 3-phase PWM), no TSIP or CTSU. | Targeted at inverter drives and servo controllers requiring advanced PWM timing and encoder interfaces - not suitable for HMI or secure firmware use cases. | Choose only for motor-centric applications; lacks security and touch features required by R5F56719DGFP#10's target use cases. |
Compared with R5F56719DGFP#10, R5F56709DFB#30 reduces footprint and cost but sacrifices SDHI/QSPIX for field-upgradable storage, while R5F566TEBDFP#30 trades security and HMI features for enhanced motor control peripherals - neither is pin-compatible, and both require PCB redesign and firmware adaptation.
Availability
R5F56719DGFP#10 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, home automation gateways, and medical patient monitors requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F56719DGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX671 Group - including R5F56719DGFP#10 - was designed for high-integrity industrial applications demanding real-time performance, functional safety (IEC60730), cybersecurity (TSIP), and rich human-machine interface capabilities.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F56719DGFP#10?
The R5F56719DGFP#10 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark points under benchmark conditions. This performance stems from the RXv3 CPU core's dual-issue pipeline, 16 general-purpose 32-bit registers, and zero-wait-state access to 384 KB SRAM - enabling deterministic real-time response in industrial control loops.
Does the R5F56719DGFP#10 support secure firmware updates and cryptographic acceleration?
Yes, the R5F56719DGFP#10 integrates Trusted Secure IP (TSIP) with hardware-accelerated AES128/192/256, RSA, ECC, SHA256, and a true random number generator (TRNG). These features enable secure boot, encrypted firmware updates, and TLS offload - all verified against IEC62443-3-3 SL2 requirements without external security chips.
What package type and pin count does the R5F56719DGFP#10 use?
The R5F56719DGFP#10 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package with 20 × 20 mm body size and 0.50 mm pitch. This package supports 113 general-purpose I/O pins (including 20 with 5-V tolerance), full JTAG/FINE debug access, and thermal pad for enhanced power dissipation in continuous 120 MHz operation.
Can the R5F56719DGFP#10 interface directly with SD cards and serial flash memory?
Yes, the R5F56719DGFP#10 includes a dedicated SD host interface (SDHI) supporting 1-/4-bit SD/SDIO buses at up to 25 MB/s, and a Quad-SPI memory interface (QSPIX) capable of fetching code directly from external serial flash. Both interfaces feature hardware CRC, DMA support, and error interrupt reporting - eliminating need for external glue logic.
How does the R5F56719DGFP#10 support IEC60730 Class B compliance for household appliances?
The R5F56719DGFP#10 provides built-in IEC60730 Class B support via oscillation-stoppage detection, hardware CRC calculation unit, windowed independent watchdog timer (IWDTa), ADC self-diagnostic function, and register write protection. These features are documented in Renesas' AN2651 application note and reduce certification effort for white goods and HVAC controllers.
R5F56719DGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 80
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F56719DGFP#10 FAQ
1.How can I place an order for R5F56719DGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F56719DGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F56719DGFP#10 reliable?
The price and inventory of R5F56719DGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F56719DGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F56719DGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F56719DGFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F56719DGFP#10?
R5F56719DGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F56719DGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F56719DGFP#10?
For technical support, including R5F56719DGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F56719DGFP#10 requirements.
6.How does Aetrix verify that R5F56719DGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F56719DGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F56719DGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F56719DGFP#10?
All R5F56719DGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F56719DGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F56719DGFP#10 part is unused and in its original packaging.
Return procedure for R5F56719DGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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