Renesas R5F56719HGLE#20
- Part No.:
- R5F56719HGLE#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F56719HGLE#20.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,645
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F56719HGLE#20 from Renesas is a 32-bit RXv3 microcontroller operating at 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control and secure firmware updates.
For engineers reviewing the R5F56719HGLE#20 datasheet, R5F56719HGLE#20 pinout, R5F56719HGLE#20 application, or R5F56719HGLE#20 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-B (144-pin LQFP), validated peripheral timing relationships, and two confirmed alternative MCUs with documented functional trade-offs for IEC60730-compliant embedded designs.
Technical Context
The R5F56719HGLE#20 implements the RXv3 CPU core with 113 instructions including DSP and IEEE-754 double-precision floating-point operations, supporting 707 CoreMark at 120 MHz. Its memory subsystem includes dual-bank 2 MB flash enabling background programming while executing from alternate bank, and 384 KB zero-wait-state SRAM synchronized to ICLK at full 120 MHz.
Peripherals are clocked across four independent domains: ICLK (up to 120 MHz for CPU/QSPIX), PCLKA (up to 120 MHz for MTU/RSPI/RIICHS), PCLKB (up to 60 MHz for most timers/A/D), and PCLKC/PCLKD (up to 60 MHz for S12AD units). The ELC enables hardware-triggered inter-module coordination without CPU intervention - critical for deterministic real-time response in motor control and power conversion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark, double-precision FPU, MPU, 16 register banks |
| Memory | 2 MB code flash (dual-bank, BGO), 8 KB data flash (100k cycles), 384 KB SRAM (no wait @120 MHz) |
| Timers | MTU3a (9 channels), TPUa (6 channels), CMTW (2×32-bit), IWDTa (14-bit, dedicated 120-kHz oscillator) |
| Connectivity | CAN (2 ch, 32 mailboxes/ch), USB 2.0 FS (host/function/OTG), SDHI (25 MB/s), QSPIX (fetch from serial flash) |
| Analog & Sensing | S12AD (2 units: 8+12 ch, 0.48 µs/ch @12-bit), CTSU (17 self-capacitance keys), on-die temp sensor (±1°C) |
| Security & Compliance | TSIP (AES128/192/256, RSA, ECC, TRNG, SHA256), IEC60730 self-test features (CRC, A/D diag, OSC stop detection) |
| Package & Temp | PLQP0144KA-B (144-pin LQFP, 20×20 mm, 0.5-mm pitch), G-grade (–40°C to +105°C) |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.50-mm lead pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog domain supplies (2.7–3.6 V); AVCC0/AVCC1 independently decoupled for ADC stability |
| VBATT | Backup power input | Enables RTC, backup registers, and sub-clock oscillator during main power loss |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator; required for high-accuracy system clock and USB timing |
| RTCIN/RTCOUT | Sub-clock oscillator terminals | Connects 32.768 kHz crystal for battery-backed RTC and low-power wake-up timing |
| TXD0/RXD0 | SCI0 asynchronous interface | Dedicated UART pins for bootloader communication or debug console (supports LIN format) |
| TXD1/RXD1 | SCI1 asynchronous interface | Second UART channel for host MCU bridging or sensor telemetry |
| CAN0TX/CAN0RX | CAN channel 0 differential pair | ISO11898-1 compliant physical layer interface; requires external transceiver and termination |
| USB_VBUS/USB_DP/USB_DM | USB 2.0 Full-Speed interface | Integrated PHY supports host/function/OTG; VBUS detection enables automatic mode switching |
| SD0_CLK/SD0_CMD/SD0_DAT0–3 | SD host interface signals | 4-bit SD bus supporting SD memory and SDIO cards per Physical Layer Spec v3.01 |
| QSPIX_IO0–3/QSPIX_CLK/QSPIX_CS | Quad-SPI memory interface | Direct execution-from-flash capability via extended/dual/quad SPI protocols |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating runtime interruption |
| Event Link Controller (ELC) | Hardware routing of 99 internal event signals (e.g., timer overflow → ADC trigger → DMA transfer) without CPU overhead |
| Trusted Secure IP (TSIP) | On-die cryptographic accelerator supporting AES-256, RSA-2048, ECC, and true random number generation for secure boot |
| Capacitive Touch Sensing Unit (CTSU) | Self- and mutual-capacitance modes support up to 64 keys on 17 pins - no external RC network required |
| IEC60730 Class B compliance support | Integrated oscillator-stop detection, CRC calculation unit, A/D self-diagnostic, and register write protection for safety-critical firmware |
Applications
| Industrial HMI Panel | Smart Electricity Meter |
|---|---|
|
Use Scenario: Embedded display controller with touch UI, real-time energy measurement, and secure remote firmware update over cellular modem. IC Role / Device Role / Timing Role: Main application processor managing GUI rendering, SD card logging, QSPIX-booted firmware, and CAN-based meter communication stack. Use Value: Dual-bank flash enables field-upgradable firmware without service interruption; TSIP secures OTA update integrity and prevents cloning. |
Use Scenario: Revenue-grade meter with tamper detection, temperature-compensated metrology, and DLMS/COSEM protocol stack. IC Role / Device Role / Timing Role: System-on-chip handling metrology ADC sampling, RTC time-stamping, secure key storage, and PLC/RF communication interface. Use Value: On-die temperature sensor feeds calibration data to S12AD; CTSU enables sealed front-panel touch controls; IEC60730 diagnostics satisfy utility certification requirements. |
| Home Energy Gateway | Motor Drive Control Unit |
|
Use Scenario: Multi-protocol gateway aggregating Zigbee, BLE, and M-Bus sensors, forwarding data to cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Protocol translation hub using USB host for dongles, SDHI for local caching, and multiple SCI/RSPI channels for sensor interfaces. Use Value: 13-channel SCI support enables concurrent legacy sensor buses; SDHI's 25 MB/s speed ensures rapid log uploads during maintenance windows. |
Use Scenario: Compact inverter controller for HVAC compressors with field-oriented control, current sensing, and fault protection. IC Role / Device Role / Timing Role: Real-time motion controller synchronizing PWM outputs (MTU3a), ADC sampling (S12AD), and gate driver enable signals via POE3a. Use Value: ELC-triggered ADC-to-PWM latency <1 µs enables precise current loop closure; IWDTa with window function guarantees fail-safe shutdown on software hang. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F56709HGLE#20 | Same RX671 Group, 1 MB flash, 256 KB SRAM, identical peripherals and pinout | Lower memory capacity suits cost-sensitive designs with smaller firmware footprints | Select when application firmware fits within 1 MB and BOM cost reduction is prioritized over future scalability |
| R5F566TEHDFP#30 | RX66T Group, 160 MHz, 1 MB flash, optimized for motor control (32-bit MTU3b, 3-phase PWM, encoder interfaces) | Lacks SDHI, QSPIX, USB OTG, and CTSU; adds advanced PWM dead-time compensation and position feedback support | Prefer for servo/inverter applications where motor control precision outweighs connectivity and HMI features |
Compared with R5F56719HGLE#20, the R5F56709HGLE#20 offers identical timing, packaging, and peripheral compatibility at reduced memory density, while the R5F566TEHDFP#30 trades general-purpose connectivity for specialized motor control acceleration - making the R5F56719HGLE#20 optimal for mixed-signal, multi-interface industrial edge nodes.
Availability
R5F56719HGLE#20 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, home energy gateways, and motor drive control units requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F56719HGLE#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX671 Group - including R5F56719HGLE#20 - was designed for high-integrity industrial applications demanding real-time performance, security, and rich connectivity in extended temperature environments.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F56719HGLE#20?
The R5F56719HGLE#20 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's efficient instruction pipeline, double-precision FPU, and zero-wait-state access to 384 KB SRAM - enabling deterministic real-time execution in demanding industrial control loops.
Does the R5F56719HGLE#20 support secure firmware updates, and how is it implemented?
Yes, the R5F56719HGLE#20 supports secure firmware updates via its Trusted Secure IP (TSIP) module, which provides hardware-accelerated AES-256 encryption, SHA256 hashing, and true random number generation. Firmware images are decrypted and authenticated in-system before being written to the dual-bank flash - ensuring integrity and confidentiality during over-the-air or local updates.
What package type and pin count does the R5F56719HGLE#20 use?
The R5F56719HGLE#20 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package measuring 20 × 20 mm with 0.50-mm pitch and an exposed thermal pad. This package supports 113 general-purpose I/O pins, including 20 with 5-V tolerance, and is rated for operation from –40°C to +105°C (G-grade).
Can the R5F56719HGLE#20 directly interface with SD cards and serial flash memory?
Yes, the R5F56719HGLE#20 integrates a full SD host interface (SDHI) supporting 1- and 4-bit SD/SDIO buses at up to 25 MB/s, and a Quad-SPI memory interface (QSPIX) capable of executing code directly from external serial flash. Both interfaces are production-ready with built-in CRC error checking and DMA support - eliminating need for external bridge ICs.
How does the R5F56719HGLE#20 meet IEC60730 Class B safety requirements?
The R5F56719HGLE#20 includes dedicated hardware features for IEC60730 Class B compliance: oscillation-stoppage detection, CRC calculation unit, self-diagnostic A/D converter test, register write protection, and independent watchdog timer (IWDTa) with windowed refresh. These are documented in Renesas' Functional Safety Manual R01UM0577EJ0100 and validated for use in certified appliances and industrial controllers.
R5F56719HGLE#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F56719HGLE#20 FAQ
1.How can I place an order for R5F56719HGLE#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F56719HGLE#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F56719HGLE#20 reliable?
The price and inventory of R5F56719HGLE#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F56719HGLE#20 is usually 5 days.
3.What payment methods are accepted for R5F56719HGLE#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F56719HGLE#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F56719HGLE#20?
R5F56719HGLE#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F56719HGLE#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F56719HGLE#20?
For technical support, including R5F56719HGLE#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F56719HGLE#20 requirements.
6.How does Aetrix verify that R5F56719HGLE#20 is sourced from the original manufacturer or authorized distributors?
All R5F56719HGLE#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F56719HGLE#20 meets industry standards.
7.What is the process for return or replacement of R5F56719HGLE#20?
All R5F56719HGLE#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F56719HGLE#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F56719HGLE#20 part is unused and in its original packaging.
Return procedure for R5F56719HGLE#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F56719HGLE#20 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

