Renesas R5F5671CDDBP#20
- Part No.:
- R5F5671CDDBP#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-TFBGA
- Datasheet:
-
R5F5671CDDBP#20.pdf
- Description:
- IC MCU 32BIT 1.5MB FLASH 64TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:490
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Product details
Overview
R5F5671CDDBP#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI, smart metering, and connected appliance control systems.
For engineers reviewing the R5F5671CDDBP#20 datasheet, R5F5671CDDBP#20 pinout, R5F5671CDDBP#20 application, or R5F5671CDDBP#20 equivalent, this page delivers verified technical context, package mapping, real-world use cases, and validated alternative options for functional replacement in safety-aware embedded designs.
Technical Context
The R5F5671CDDBP#20 implements the RXv3 CPU core with 113 instructions, 16 general-purpose 32-bit registers, and dual-precision floating-point coprocessor supporting 21 FP64 instructions. It integrates memory protection unit (MPU) with eight configurable regions and supports little- or big-endian data arrangement.
Its clock system combines external crystal (8–24 MHz), sub-clock oscillator (32.768 kHz), and internal oscillators (LOCO/HOCO/IWDT-dedicated), enabling independent domain clocks: ICLK up to 120 MHz, PCLKA/PCLKB up to 120/60 MHz, and ADCLK up to 60 MHz per A/D unit - critical for deterministic timing in mixed-signal applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark score - enables real-time deterministic execution of complex control algorithms. |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k erase cycles), 384 KB SRAM (no-wait @120 MHz) - supports secure firmware updates and large buffer handling. |
| FPU | Double-precision IEEE-754 compliant - required for high-accuracy sensor fusion, motor control math, and cryptographic operations. |
| Peripherals | 2× CAN FD-capable channels (32 mailboxes), USB 2.0 FS host/function/OTG, SDHI (25 MB/s), QSPIX (fetch from serial flash), 2× 12-bit S12AD (8+12 ch), CTSU (17-key self-cap) |
| Security | Trusted Secure IP (TSIP): AES128/192/256, RSA, ECC, TRNG, SHA256, key copy prevention - meets IEC60730 Class B requirements. |
| Power & Temp | 2.7–3.6 V supply, –40°C to +85°C (D-version), four low-power modes including deep software standby with 4 KB backup RAM - suitable for battery-backed industrial nodes. |
Pinout & Package
Package: PLQP0144KA-B (144-pin LQFP, 20 × 20 mm, 0.50-mm pitch). Pin count and I/O configuration match RX671 Group specification for 144-pin LFQFP: 113 programmable I/O pins, 20 with 5-V tolerance, full pull-up and open-drain support.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains enable noise isolation for ADC and RTC; AVCC1 powers S12AD unit 1 and temperature sensor. |
| VBATT | Backup power input | Supplies RTC, sub-clock oscillator, and backup registers during main power loss - enables timekeeping in deep standby. |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; paired with PLL for stable 120 MHz ICLK - essential for USB timing and high-speed peripherals. |
| RTCIN / RTCOUT | 32.768 kHz sub-clock oscillator | Connects to external tuning fork crystal; provides precise timebase for RTC calendar, alarm, and time-capture functions. |
| TXD0 / RXD0 | SCI0 asynchronous UART | Dedicated debug/programming interface in boot mode; supports baud-rate generation via TMR for robust host communication. |
| TXD1 / RXD1 | SCI1 asynchronous UART | Configurable as LIN-compliant interface (SCIh) - used for automotive body control or industrial fieldbus bridging. |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 Full-Speed PHY | Integrated transceiver requires no external resistors; supports host/function/OTG with 2 KB on-chip buffer - enables plug-and-play connectivity. |
| SD0_CLK / SD0_CMD / SD0_DAT0–3 | SD host interface signals | 1- or 4-bit SD bus supporting SD Memory Card Ver. 3.01 and SDIO Ver. 3.00 - enables local data logging and firmware storage. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware update: one bank executes while the other is reprogrammed - eliminates system downtime during OTA upgrades. |
| Event Link Controller (ELC) | 99 internal event signals routed without CPU intervention - reduces latency for time-critical actions like PWM-triggered ADC sampling. |
| Capacitive Touch Sensing Unit (CTSU) | Supports 17-key self-capacitance or 64-key mutual-capacitance matrix - enables robust, low-power touch HMI without external ICs. |
| IEC60730 compliance suite | Oscillation-stop detection, CRC-accelerated self-test, IWDT windowing, register write protection - simplifies Class B certification for home appliances. |
| Trusted Memory (TM) function | Restricts code execution to protected TM target area and prevents read-out of sensitive firmware - enforces secure boot integrity. |
Applications
| Industrial HMI Panel | Smart Energy Meter |
|---|---|
|
Use Scenario: Embedded touchscreen display with real-time energy monitoring, tariff switching, and tamper detection. IC Role / Device Role / Timing Role: Main application controller managing GUI rendering, CAN-based utility comms, SDHI data logging, and CTSU touch interface. Use Value: Dual-bank flash enables field-upgradable UI firmware; TSIP secures tariff keys; RTC with VBATT backup maintains billing timestamps across outages. |
Use Scenario: DIN-rail mounted electricity meter with pulse counting, harmonic analysis, and remote firmware update over PLC or RF. IC Role / Device Role / Timing Role: Central processing unit executing IEC62056 protocol stack, 12-bit ADC sampling at 10 kSPS, and CAN/USB diagnostics. Use Value: 120 MHz RXv3 core handles FFT-based harmonic calculation; dual 12-bit S12AD units support simultaneous voltage/current sampling; TSIP signs firmware images. |
| Connected Home Appliance | Motor Control Gateway |
|
Use Scenario: Wi-Fi-enabled washing machine with load sensing, detergent dosing, and cloud telemetry via BLE bridge. IC Role / Device Role / Timing Role: System-on-module MCU coordinating motor drivers, temperature sensor, capacitive buttons, and USB/SDHI for diagnostics. Use Value: CTSU replaces mechanical buttons with waterproof interface; 384 KB SRAM buffers sensor logs; QSPIX fetches UI assets from external flash. |
Use Scenario: HVAC inverter gateway aggregating CAN bus data from multiple fan/compressor controllers and reporting to building BMS. IC Role / Device Role / Timing Role: Real-time coordinator using MTU3a PWM outputs, CAN mailbox filtering, and ELC-triggered ADC sampling for current feedback. Use Value: Complementary PWM mode with dead-time compensation drives 3-phase IGBTs; 2× CAN channels isolate fieldbus traffic; MPU isolates safety-critical firmware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EDDFP#30 | Same RX671 Group, 100-pin LQFP, 1.5 MB flash, 256 KB SRAM, no SDHI or QSPIX - lower peripheral count. | Suitable for cost-sensitive motor control where SD/flash boot not required; lacks capacitive touch and USB OTG. | Select when footprint and BOM cost constrain design, and full RX671 peripheral set is unnecessary. |
| R5F566TEADFP#30 | RX66T Group, 100-pin LQFP, 120 MHz, 1 MB flash, 192 KB SRAM, optimized for motor control (3× MTU3, 3× CMTW), no SDHI/CTSU/TSIP. | Targeted at servo/inverter applications requiring high-resolution PWM and encoder capture - lacks security and HMI features. | Choose for dedicated motor drive where TSIP, touch, and SD storage are irrelevant and PWM channel density is critical. |
Compared with R5F5671CDDBP#20, the R5F5670EDDFP#30 reduces package size and peripheral count for simpler control tasks, while the R5F566TEADFP#30 trades HMI/security features for enhanced motor timing resources - making each viable only in narrowly defined subsystem roles.
Availability
R5F5671CDDBP#20 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, and connected appliance control requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F5671CDDBP#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and IoT markets.
The RX671 Group is designed for safety-certifiable, feature-rich embedded applications demanding real-time performance, cryptographic security, and human-machine interaction - targeting smart infrastructure and connected devices.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671CDDBP#20?
The R5F5671CDDBP#20 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark points under benchmark conditions. This performance stems from the RXv3 CPU core's efficient instruction pipeline and dual-precision FPU integration - enabling R5F5671CDDBP#20 to execute complex control loops and signal processing tasks within strict real-time deadlines.
Does the R5F5671CDDBP#20 support secure firmware updates and cryptographic operations?
Yes, the R5F5671CDDBP#20 includes Trusted Secure IP (TSIP) with AES128/192/256, RSA, ECC, SHA256, and a true-random number generator. Its dual-bank flash architecture allows background programming while executing from the active bank - ensuring R5F5671CDDBP#20 can perform authenticated, encrypted over-the-air updates without service interruption.
What package type and pin count does the R5F5671CDDBP#20 use?
The R5F5671CDDBP#20 uses the PLQP0144KA-B package: a 144-pin LQFP measuring 20 × 20 mm with 0.50-mm pitch. It provides 113 general-purpose I/O pins, 20 of which are 5-V tolerant, along with dedicated pins for USB, SDHI, CAN, QSPIX, and CTSU - matching the full peripheral complement of the RX671 Group's 144-pin variant.
Can the R5F5671CDDBP#20 operate in low-power modes with RTC and backup RAM retention?
Yes, the R5F5671CDDBP#20 supports four low-power modes, including deep software standby where the 4 KB standby RAM and RTC remain powered via VBATT. In this mode, the sub-clock oscillator continues running, preserving calendar time and alarm functionality - allowing R5F5671CDDBP#20 to wake on timer or external event while consuming minimal current.
Which communication interfaces are integrated into the R5F5671CDDBP#20 for industrial connectivity?
The R5F5671CDDBP#20 integrates two ISO11898-1-compliant CAN channels (32 mailboxes each), USB 2.0 Full-Speed host/function/OTG, SD host interface (25 MB/s), QSPIX for serial flash boot, three I²C channels (including RIICHS at 3.4 Mbps), and multiple SCI/RSPI peripherals - enabling R5F5671CDDBP#20 to serve as a central hub in multi-protocol industrial networks.
R5F5671CDDBP#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-TFBGA
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 43
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 10x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671CDDBP#20 FAQ
1.How can I place an order for R5F5671CDDBP#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671CDDBP#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671CDDBP#20 reliable?
The price and inventory of R5F5671CDDBP#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671CDDBP#20 is usually 5 days.
3.What payment methods are accepted for R5F5671CDDBP#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671CDDBP#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671CDDBP#20?
R5F5671CDDBP#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671CDDBP#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671CDDBP#20?
For technical support, including R5F5671CDDBP#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671CDDBP#20 requirements.
6.How does Aetrix verify that R5F5671CDDBP#20 is sourced from the original manufacturer or authorized distributors?
All R5F5671CDDBP#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671CDDBP#20 meets industry standards.
7.What is the process for return or replacement of R5F5671CDDBP#20?
All R5F5671CDDBP#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671CDDBP#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671CDDBP#20 part is unused and in its original packaging.
Return procedure for R5F5671CDDBP#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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