Renesas R5F5671CHDFB#30
- Part No.:
- R5F5671CHDFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5671CHDFB#30.pdf
- Description:
- IC MCU 32BIT 1.5MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:180
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5671CHDFB#30 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control and secure firmware updates.
For engineers reviewing the R5F5671CHDFB#30 datasheet, R5F5671CHDFB#30 pinout, R5F5671CHDFB#30 application, or R5F5671CHDFB#30 equivalent, key selection considerations include its 144-pin LFQFP package (PLQP0144KA-B), -40°C to +85°C temperature grade, TSIP-based AES256/SHA256 encryption, 12-bit dual A/D converter with self-diagnostic capability, and IEC60730-compliant safety features for Class B appliance control.
Technical Context
The R5F5671CHDFB#30 implements the RXv3 CPU core with 113 instructions, 16 general-purpose 32-bit registers, and dual-precision FPU supporting 21 double-precision floating-point instructions. It integrates a memory protection unit (MPU) with eight configurable regions and supports little- or big-endian data arrangement.
Its clock system combines external crystal (8–24 MHz), sub-clock (32.768 kHz), and internal oscillators (LOCO/HOCO/IWDT-dedicated), enabling independent domain clocks: ICLK up to 120 MHz for CPU/QSPIX, PCLKA up to 120 MHz for MTU/RSPI/RIICHS, and PCLKB up to 60 MHz for most peripherals including S12AD units.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark score - enables deterministic real-time execution in motor control and protocol stacks. |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k write cycles), 384 KB SRAM (no-wait @120 MHz) - supports field firmware updates without halting operation. |
| FPU | Double-precision IEEE-754 coprocessor with 16×64-bit registers - accelerates sensor fusion, digital power control, and cryptographic math. |
| Security | Trusted Secure IP (TSIP): AES128/192/256, RSA, ECC, SHA256, TRNG, key protection - meets IEC60730 Class B and IoT device attestation requirements. |
| Analog | Dual 12-bit S12AD: Unit 0 (8 ch), Unit 1 (12 ch); 0.48 µs conversion time; self-diagnostic & disconnection detection - ensures reliable sensor monitoring in safety-critical systems. |
| Interfaces | CAN (2 ch, 32 mailboxes), USB 2.0 FS (host/function/OTG), SDHI (25 MB/s), QSPIX (fetch from serial flash), RIICHS (3.4 Mbps) - enables connectivity in industrial gateways and edge nodes. |
| Package | PLQP0144KA-B: 144-pin LFQFP, 20 × 20 mm, 0.50-mm pitch, -40°C to +85°C - compatible with standard reflow profiles and high-density PCB layouts. |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 × 20 mm body, 0.50-mm lead pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | 2.7–3.6 V single-supply operation; separate analog domains enable clean ADC reference and noise isolation. |
| VBATT | Backup power input | Enables RTC and backup registers to retain state during main power loss - critical for energy meter timestamping and tamper logging. |
| RES# | Active-low reset input | Hardware reset assertion; combined with internal POR/LVD for robust power sequencing in industrial environments. |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise timing; paired with PLL for stable 120 MHz ICLK generation. |
| MD0 / MD1 | Mode setting pins | Configure boot mode (SCI/USB/FINE) and operating mode (single-chip/ROM-enabled extended) at power-on reset. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O ports | 114 total GPIOs; 20 pins 5-V tolerant; programmable pull-up, open-drain, and drive strength - simplifies level-shifting and direct sensor/actuator interfacing. |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Class B Support | Oscillation-stop detection, CRC-accelerated self-test, register write protection, and A/D self-diagnostic - reduces certification effort for household appliances and industrial controls. |
| Capacitive Touch Sensing (CTSU) | 17-key self-capacitance or 64-key mutual-capacitance matrix - enables robust, low-power HMI on panels without mechanical buttons. |
| Event Link Controller (ELC) | 99 internal event signals routed without CPU intervention - enables hardware-synchronized PWM-triggered ADC sampling and fault-responsive GPIO toggling. |
| Low-Power Modes | Four modes: Sleep, All-module clock stop, Software standby, Deep software standby - achieves µA-level current in deep standby with RTC + 4 KB RAM retention. |
| Secure Boot & Firmware Updates | Trusted Memory (TM) function restricts code execution to protected flash areas; dual-bank flash allows atomic firmware swap - prevents bricking during OTA updates. |
Applications
| Industrial HMI Panel | Smart Energy Meter |
|---|---|
Use Scenario: Touch-enabled display controller with real-time data visualization, local logging, and remote communication via CAN/USB. IC Role / Device Role / Timing Role: Main application processor executing GUI framework, managing CTSU touch inputs, and coordinating SDHI/USB data transfers. Use Value: Integrated QSPIX enables fast boot from external flash; TSIP secures firmware updates; 384 KB SRAM hosts graphics buffers and protocol stacks without external memory. | Use Scenario: Revenue-grade meter with metrology ASIC interface, tamper detection, RTC timestamping, and PLC/GPRS communication. IC Role / Device Role / Timing Role: System controller handling metrology data aggregation, secure storage, and communication stack management. Use Value: Dual 12-bit A/D converters monitor auxiliary sensors; VBATT-backed RTC maintains billing timestamps across outages; CAN interface connects to concentrator networks. |
| Home Appliance Control | Industrial Gateway |
Use Scenario: Washing machine MCU managing motor control (FOC), water valve actuation, user interface, and safety monitoring per IEC60730. IC Role / Device Role / Timing Role: Safety-certified main controller executing motor algorithms, reading temperature/pressure sensors, and validating system integrity. Use Value: MPU enforces memory partitioning; self-diagnostic A/D and oscillation detection satisfy Class B requirements; 120 MHz CPU handles real-time FOC loops. | Use Scenario: Edge gateway aggregating Modbus RTU, CANopen, and BLE sensor data, then forwarding to cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Protocol translation hub with multiple serial interfaces, secure TLS offload, and local rule engine. Use Value: 13-channel SCI + 2×CAN + QSPIX + SDHI supports heterogeneous fieldbus integration; TSIP accelerates TLS handshake and firmware signing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EHDFB#30 | Same RX671 Group, 144-pin LFQFP, but with 1.5 MB flash and no TSIP - lacks AES/SHA/TRNG acceleration. | Suitable for cost-sensitive designs where cryptographic functions are handled externally or omitted. | Select when security features are unnecessary and flash capacity ≤1.5 MB suffices. |
| R5F566TEHDFB#30 | RX66T Group part: 160 MHz CPU, 1 MB flash, no TSIP, enhanced MTU3 for motor control, but no SDHI or QSPIX. | Optimized for inverter-driven motor control with higher PWM resolution; lacks connectivity for gateway use cases. | Prefer for servo drives or HVAC compressors needing >120 MHz timing precision and advanced PWM, not connectivity. |
Compared with R5F5671CHDFB#30, the R5F5670EHDFB#30 trades TSIP and 2 MB flash for lower cost, while the R5F566TEHDFB#30 sacrifices SDHI/QSPIX/TSIP to deliver higher CPU frequency and motor-control-specific timers - making R5F5671CHDFB#30 the balanced choice for secure, connected industrial edge devices.
Availability
R5F5671CHDFB#30 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, home appliance control, and edge gateway applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F5671CHDFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX671 Group targets high-integrity industrial applications demanding real-time performance, functional safety, and secure connectivity - with R5F5671CHDFB#30 optimized for systems requiring dual A/D, capacitive touch, and IEC60730 compliance.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F5671CHDFB#30?
The R5F5671CHDFB#30 operates at a maximum frequency of 120 MHz using the 32-bit RXv3 CPU core. It delivers 707 CoreMark performance and includes 16 general-purpose 32-bit registers, dual-precision IEEE-754 FPU, and support for both little- and big-endian data formats - enabling high-efficiency deterministic execution in real-time control applications.
Does the R5F5671CHDFB#30 support secure firmware updates and cryptographic operations?
Yes, the R5F5671CHDFB#30 integrates Trusted Secure IP (TSIP) supporting AES128/192/256, SHA256, RSA, ECC, and a true-random number generator (TRNG). Its dual-bank flash architecture enables atomic firmware updates, and Trusted Memory (TM) restricts code execution to protected areas - ensuring secure boot and OTA update integrity for industrial and IoT deployments.
What package type and pin count does the R5F5671CHDFB#30 use?
The R5F5671CHDFB#30 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package with 20 × 20 mm body size, 0.50-mm lead pitch, and exposed thermal pad. It is rated for -40°C to +85°C operation and complies with RoHS and JEDEC standards for automated assembly.
How many analog-to-digital converter channels does the R5F5671CHDFB#30 provide, and what are their key capabilities?
The R5F5671CHDFB#30 integrates two 12-bit A/D converter units: S12AD0 with 8 channels and S12AD1 with 12 channels. Both support 8/10/12-bit resolution, 0.48 µs conversion time, self-diagnostic voltage generation, analog input disconnection detection, and trigger sources including MTU/TPU timers and external events - meeting precision sensing needs in metering and motor control.
Which communication interfaces are integrated into the R5F5671CHDFB#30, and what are their maximum speeds?
The R5F5671CHDFB#30 integrates CAN (2 channels, ISO11898-1 compliant), USB 2.0 Full-Speed (12 Mbps host/function/OTG), SD host interface (25 MB/s), QSPIX (120 MHz), RIICHS (3.4 Mbps), and up to 13 serial channels (SCI/SCIm/RSCI) - providing comprehensive connectivity for industrial gateways, HMIs, and smart meters without external transceivers or bridge ICs.
R5F5671CHDFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 113
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671CHDFB#30 FAQ
1.How can I place an order for R5F5671CHDFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671CHDFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671CHDFB#30 reliable?
The price and inventory of R5F5671CHDFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671CHDFB#30 is usually 5 days.
3.What payment methods are accepted for R5F5671CHDFB#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671CHDFB#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671CHDFB#30?
R5F5671CHDFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671CHDFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671CHDFB#30?
For technical support, including R5F5671CHDFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671CHDFB#30 requirements.
6.How does Aetrix verify that R5F5671CHDFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F5671CHDFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671CHDFB#30 meets industry standards.
7.What is the process for return or replacement of R5F5671CHDFB#30?
All R5F5671CHDFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671CHDFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671CHDFB#30 part is unused and in its original packaging.
Return procedure for R5F5671CHDFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5671CHDFB#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

